DataSheet.jp

V62C1162048L-100T の電気的特性と機能

V62C1162048L-100TのメーカーはMosel Vitelic Corpです、この部品の機能は「Ultra Low Power 128K x 16 CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 V62C1162048L-100T
部品説明 Ultra Low Power 128K x 16 CMOS SRAM
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




このページの下部にプレビューとV62C1162048L-100Tダウンロード(pdfファイル)リンクがあります。
Total 11 pages

No Preview Available !

V62C1162048L-100T Datasheet, V62C1162048L-100T PDF,ピン配置, 機能
Features
• Low-power consumption
- Active: 35mA ICC at 70ns
- Stand-by: 10 µA (CMOS input/output)
2 µA (CMOS input/output, L version)
• 70/85/100/120 ns access time
• Equal access and cycle time
• Single +1.8V to2.2V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
• Available in 44 pin TSOPII / 48-fpBGA / 48-µBGA
V62C1162048L(L)
Ultra Low Power
128K x 16 CMOS SRAM
Functional Description
The V62C1162048L is a Low Power CMOS Static
RAM organized as 131,072 words by 16 bits. Easy
Memory expansion is provided by an active LOW (CE)
and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
Logic Block Diagram
TSOPII / 48-fpBGA / 48-µBGA (See nest page)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
Pre-Charge Circuit
Memory Array
1024 X 2048
Vcc
Vss
Data
Cont I/O Circuit
Data
Cont
Column Select
A10 A11 A12 A13 A14 A15 A16
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
I/O1 7
I/O2 8
I/O3 9
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A16 18
A15 19
A14 20
A13 21
A12 22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
REV. 1.2 May 2001 V62C1162048L(L)
1

1 Page





V62C1162048L-100T pdf, ピン配列
V62C1162048L(L)
Absolute Maximum Ratings *
Parameter
Voltage on Any Pin Relative to Gnd
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
Symbol
Vt
PT
Tstg
Tbias
Minimum
-0.5
-55
-40
Maximum
+4.0
1.0
+150
+85
Unit
V
W
0C
0C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE OE WE BLE BHE I/O1-I/O8 I/O9-I/O16
H X X X X High-Z
High-Z
L L H L H Data Out High-Z
L L H H L High-Z Data Out
L L H L L Data Out Data Out
L X L L L Data In Data In
L X L L H Data In High-Z
L X L H L High-Z Data In
L H H X X High-Z
High-Z
L X X H H High-Z High-Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Mode
Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Output Disable
Output Disable
* Key: X = Don’t Care, L = Low, H = High
Recommended Operating Conditions (TA = 0oC to +70oC / -40oC to 85oC**)
Parameter
Supply Voltage
Input Voltage
Symbol Min
Typ
Max
Unit
VCC 1.8 2.0
Gnd 0.0 0.0
2.2
0.0
V
V
VIH 1.6 - VCC + 0.2 V
VIL -0.5* - 0.4 V
* VIL min = -2.0V for pulse width less than tRC/2.
** For Industrial Temperature
REV. 1.2 May 2001 V62C1162048L(L)
3


3Pages


V62C1162048L-100T 電子部品, 半導体
V62C1162048L(L)
Timing Waveform of Read Cycle 1 (Address Controlled)
Address
Data Out
tOH
Previous Data Valid
tRC
tAA
Timing Waveform of Read Cycle 2
Address
CE
(BLE/BHE)
OE
Data Out
High-Z
tAA
tACE
tLZ(4,5)
tBA
tBLZ(4,5)
tOE
tOLZ
tRC
Data Valid
tHZ(3,4,5)
tBHZ(3,4,5)
tOHZ
Data Valid
tOH
Notes (Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels.
4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = VIL.
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see AC Test Condition, Figure A.
REV. 1.2 May 2001 V62C1162048L(L)
6

6 Page



ページ 合計 : 11 ページ
 
PDF
ダウンロード
[ V62C1162048L-100T データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
V62C1162048L-100B

Ultra Low Power 128K x 16 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp
V62C1162048L-100M

Ultra Low Power 128K x 16 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp
V62C1162048L-100T

Ultra Low Power 128K x 16 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap