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V62C1161024L-85T の電気的特性と機能

V62C1161024L-85TのメーカーはMosel Vitelic Corpです、この部品の機能は「Ultra Low Power 64K x 16 CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 V62C1161024L-85T
部品説明 Ultra Low Power 64K x 16 CMOS SRAM
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




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V62C1161024L-85T Datasheet, V62C1161024L-85T PDF,ピン配置, 機能
V62C1161024L(L)
Ultra Low Power
64K x 16 CMOS SRAM
Features
Functional Description
• Ultra Low-power consumption
- Active: 30mA ICC at 70ns
- Stand-by: 5 µA (CMOS input/output)
1 µA (CMOS input/output, L version)
• 70/85/100/120 ns access time
• Equal access and cycle time
• Single +1.8V to 2.2V Power Supply
• Tri-state output
• Automatic power-down when deselected
The V62C1161024L is a Low Power CMOS Static RAM
organized as 65,536 words by 16 bits. Easy memory exp-
ansion is provided by an active LOW (CE) and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
• Available in 44 pin TSOP (II) Package
Logic Block Diagram
TSOP(II)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
Pre-Charge Circuit
Memory Array
1024 X 1024
Vcc
Vss
Data
Cont I/O Circuit
Data
Cont
Column Select
A10 A11 A12 A13 A14 A15
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
I/O1 7
I/O2 8
I/O3 9
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A15 18
A14 19
A13 20
A12 21
NC 22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
REV. 1.1 April 2001 V62C1161024L(L)
1

1 Page





V62C1161024L-85T pdf, ピン配列
V62C1161024L(L)
DC Operating Characteristics (Vcc = 2V+10%, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Parameter
Input Leakage Current
Output Leakage
Current
Sym Test Conditions
IILI
Vcc = Max,
Vin = Gnd to Vcc
IILO
CE = VIH or Vcc= Max,
VOUT = Gnd to Vcc
-70 -85 -100 -120
Unit
Min Max Min Max Min Max Min Max
- 1 - 1 - 1 - 1 µA
- 1 - 1 - 1 - 1 µA
Operating Power
Supply Current
ICC CE = VIL , VIN = VIH or VIL , - 3 - 3 - 3 - 3 mA
IOUT = 0
Average Operating
Current
ICC1 IOUT = 0mA,
Min Cycle, 100% Duty
- 30 - 25 - 20 - 20 mA
ICC2 CE < 0.2V
- 3 - 3 - 3 - 3 mA
IOUT = 0mA,
Cycle Time=1µs, Duty=100%
Standby Power Supply ISB CE = VIH
Current (TTL Level)
- 0.5 - 0.5 - 0.5 - 0.5 mA
Standby Power Supply ISB1 CE > Vcc - 0.2V
Current (CMOS Level)
VIN < 0.2V or
VIN > Vcc- 0.2V
L - 5 - 5 - 5 - 5 µA
LL - 1
-1
-1
- 1 µA
Output Low Voltage
VOL IOL = 2 mA
- 0.4 - 0.4 - 0.4 - 0.4 V
Output High Voltage VOH IOH = -1 mA
1.6 - 1.6 - 1.6 - 1.6 -
V
Capacitance (f = 1MHz, TA = 250C)
Parameter*
Input Capacitance
I/O Capacitance
Symbol
C in
C I/O
Test Condition
Vin = 0V
Vin = Vout = 0V
Max
7
8
Unit
pF
pF
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.4V to 1.6V
5ns
1.0V
Output Load Condition
70ns/85ns
Load for 100ns/120ns
CL = 30pf + 1TTL Load
CL = 100pf + 1TTL Load
CL*
TTL
Figure A. * Including Scope and Jig Capacitance
REV. 1.1 April 2001 V62C1161024L(L)
3


3Pages


V62C1161024L-85T 電子部品, 半導体
V62C1161024L(L)
Timing Waveform of Write Cycle 1 (Address Controlled)
tWC
Address
CE
tAW
tCW (3)
BLE/BHE
WE
Data In
Data Out
High-Z
tAS (4)
tOHZ (6)
tBW
tWP (2)
tDW
High-Z (8)
tDH
tWR (5)
tOW
Timing Waveform of Write Cycle 2 (CE Controlled)
tWC
Address
CE
tAS (4)
tAW
tCW (3)
tBW
BLE/BHE
WE
Data In
Data Out
High-Z
High-Z
tLZ
tWP (2)
tDW
tWHZ (6)
tWR (5)
tDH
High-Z (8)
Timing Waveform of Write Cycle 3 (BLE/BHE Controlled)
tWC
Address
CE
BLE/BHE
tAS (4)
tAW
tCW (3)
tBW
tWR (5)
WE
Data In
Data Out
High-Z
High-Z
tBLZ
tWP (2)
tDW
tWHZ (6)
tDH
High-Z (8)
REV. 1.1 April 2001 V62C1161024L(L)
6

6 Page



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部品番号部品説明メーカ
V62C1161024L-85T

Ultra Low Power 64K x 16 CMOS SRAM

Mosel Vitelic  Corp
Mosel Vitelic Corp


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