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V58C265164S の電気的特性と機能

V58C265164SのメーカーはMosel Vitelic Corpです、この部品の機能は「64 Mbit DDR SDRAM 2.5 VOLT 4M X 16」です。


製品の詳細 ( Datasheet PDF )

部品番号 V58C265164S
部品説明 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




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V58C265164S Datasheet, V58C265164S PDF,ピン配置, 機能
MOSEL VITELIC
V58C265164S
64 Mbit DDR SDRAM
2.5 VOLT 4M X 16
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Cycle Time (tCK2.5)
Clock Cycle Time (tCK2)
4
250 MHz
4 ns
4.8 ns
6 ns
45
225 MHz
4.5 ns
5.4 ns
6.75 ns
5
200 MHz
5 ns
6 ns
7.5 ns
55
183 MHz
5.5 ns
6.6 ns
8.25 ns
Features
I 4 banks x 1Mbit x 16 organization
I High speed data transfer rates with system
frequency up to 250 MHz
I Data Mask for Write Control (DM)
I Four Banks controlled by BA0 & BA1
I Programmable CAS Latency: 2, 2.5, 3
I Programmable Wrap Sequence: Sequential
or Interleave
I Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
I Automatic and Controlled Precharge Command
I Suspend Mode and Power Down Mode
I Auto Refresh and Self Refresh
I Refresh Interval: 4096 cycles/64 ms
I Available in 66-pin 400 mil TSOP-II
I SSTL-2 Compatible I/Os
I Double Data Rate (DDR)
I Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
I On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
I Differential clock inputs CLK and CLK
I Power supply 2.5V ± 0.2V
Description
The V58C265164S is a four bank DDR DRAM
organized as 4 banks x 1Mbit x 16. The
V58C265164S achieves high speed data transfer
rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
CLK Cycle Time (ns)
-4 -45 -5 -55
• •••
Power
Std. L
••
Temperature
Mark
Blank
V58C265164S Rev. 1.7 August 2001
1

1 Page





V58C265164S pdf, ピン配列
MOSEL VITELIC
Capacitance*
TA = 0 to 70°C, VCC = 2.5 V ± 0.2 V, f = 1 Mhz
Symbol Parameter
Max. Unit
CI1 Input Capacitance (A0 to A11)
CI2 Input Capacitance
RAS, CAS, WE, CS, CKE
5 pF
5 pF
CIO
CCLK
Output Capacitance (DQ)
Input Capacitance (CCLK, CLK)
6.5 pF
4 pF
*Note: Capacitance is sampled and not 100% tested.
V58C265164S
Absolute Maximum Ratings*
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ...........................................1.6 W
Data out current (short circuit).......................50 mA
*Note: Stresses above those listed under Absolute Maximum
Ratingsmay cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Block Diagram
Column Addresses
A0 - A7, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 256
x 16 bit
Row decoder
Memory array
Bank 1
4096 x 256
x 16 bit
Row decoder
Memory array
Bank 2
4096 x 256
x 16 bit
Row decoder
Memory array
Bank 3
4096 x 256
x 16 bit
CLK, CLK
DQS
Input buffer Output buffer
DLL
Strobe
Gen.
I/Q0-IQ15
Data Strobe
Control logic & timing generator
V58C265164S Rev. 1.7 August 2001
3


3Pages


V58C265164S 電子部品, 半導体
MOSEL VITELIC
V58C265164S
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A0 ~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
cycles are required to meet tMRD spec. The mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode
uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a Mosel Vitelic specific test
mode during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer
to the table for specific codes for various burst length, addressing modes and CAS latencies.
1. MRS can be issued only at all banks precharge state.
2. Minimum tRP is required to issue MRS command.
BA1 BA 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0 MRS
0 MRS
RFU
RFU : Must be set "0"
I/O DLL Extended Mode Register
DLL TM CAS Latency BT Burst Length Mode Register
A8 DLL Reset A7 mode
0 No
0 Normal
1 Yes
1 Test
CAS Latency
A3 Burst Type
0 Sequential
1 Interleave
Burst Length
BA0
An ~ A0
0 (Existing)MRS Cycle
1 Extended Funtions(EMRS)
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
A6 A5 A4 Latency
0 0 0 Reserve
0 0 1 Reserve
01 0
2
01 1
3
1 0 0 Reserve
1 0 1 Reserve
11 0
2.5
1 1 1 Reserve
A2 A1 A0
000
001
010
011
100
101
110
111
A1 I/O Strength
0 Full
1 Half
A0
0
1
Latency
Sequential Interleave
Reserve
Reserve
22
44
88
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
DLL Enable
Enable
Disable
Mode Register Set
012345678
CK, CK
Command
Precharge
All Banks
tCK
tRP *2
*1
Mode
Register Set
tMRD
Any
Command
V58C265164S Rev. 1.7 August 2001
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6 Page



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部品番号部品説明メーカ
V58C265164S

64 Mbit DDR SDRAM 2.5 VOLT 4M X 16

Mosel Vitelic  Corp
Mosel Vitelic Corp


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