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V54C365404VD の電気的特性と機能

V54C365404VDのメーカーはMosel Vitelic Corpです、この部品の機能は「HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4」です。


製品の詳細 ( Datasheet PDF )

部品番号 V54C365404VD
部品説明 HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




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V54C365404VD Datasheet, V54C365404VD PDF,ピン配置, 機能
MOSEL VITELIC
V54C365404VD(L)
HIGH PERFORMANCE 143/133/125 MHz
3.3 VOLT 16M X 4 SYNCHRONOUS DRAM
4 BANKS X 4Mbit X 4
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
7
143 MHz
7 ns
5.4 ns
5.5 ns
75
133 MHz
7.5 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
8
125 MHz
8 ns
7 ns
7 ns
Features
s 4 banks x 4Mbit x 4 organization
s High speed data transfer rates up to 143 MHz
s Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s Single Pulsed RAS Interface
s Data Mask for Read/Write Control
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 2, 3
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
s Multiple Burst Read with Single Write Operation
s Automatic and Controlled Precharge Command
s Random Column Address every CLK (1-N Rule)
s Suspend Mode and Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 54 Pin 400 mil TSOP-II
s LVTTL Interface
s Single +3.3 V ±0.3 V Power Supply
Description
The V54C365404VD(L) is a four bank Synchro-
nous DRAM organized as 4 banks x 4Mbit x 4. The
V54C365404VD(L) achieves high speed data trans-
fer rates up to 143 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
143 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T
Access Time (ns)
7 75 8PC
• ••
8
Power
Std. L
••
Temperature
Mark
Blank
V54C365404VD(L) Rev. 0.9 September 2001
1

1 Page





V54C365404VD pdf, ピン配列
MOSEL VITELIC
Capacitance*
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
Symbol Parameter
Max. Unit
CI1 Input Capacitance (A0 to A11)
5 pF
CI2 Input Capacitance
5 pF
RAS, CAS, WE, CS, CLK, CKE, DQM
CIO
CCLK
Output Capacitance (I/O)
Input Capacitance (CLK)
6.5 pF
4 pF
*Note: Capacitance is sampled and not 100% tested.
V54C365404VD(L)
Absolute Maximum Ratings*
Operating temperature range ................... 0 to 70°C
Storage temperature range .................-55 to 150°C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA
*Note: Stresses above those listed under Absolute Maximum
Ratingsmay cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Block Diagram
Column Addresses
A0 - A9, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 1024
x 4 bit
Row decoder
Memory array
Bank 1
4096 x 1024
x 4 bit
Row decoder
Memory array
Bank 2
4096 x 1024
x 4 bit
Row decoder
Memory array
Bank 3
4096 x 1024
x 4 bit
Input buffer Output buffer
I/O1-I/O4
Control logic & timing generator
V54C365404VD(L) Rev. 0.9 September 2001
3


3Pages


V54C365404VD 電子部品, 半導体
MOSEL VITELIC
Power On and Initialization
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the NOPstate. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200 µs is required followed by a
precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation
mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy-
cle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Opera-
tion mode field to differentiate between normal op-
eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate com-
mand after the initial power up. Any content of the
mode register can be altered by re-executing the
V54C365404VD(L)
mode set command. All banks must be in pre-
charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is re-
quired. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set op-
eration. Address input data at this timing defines pa-
rameters to be set as shown in the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select-
ed bank is activated and all of sense amplifiers as-
sociated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, tRCD, from the
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 143 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8 and full page. Column address-
es are segmented by the burst length and serial
data accesses are done within this boundary. The
first column address to be accessed is supplied at
the CAS timing and the subsequent addresses are
generated automatically by the programmed burst
length and its sequence. For example, in a burst
length of 8 with interleave sequence, if the first ad-
dress is 2, then the rest of the burst sequence is 3,
0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using
the sequential burst type and page length is a func-
tion of the I/O organisation and column addressing.
Full page burst operation do not self terminate once
the burst length has been reached. In other words,
unlike burst length of 2, 3 or 8, full page burst con-
tinues until it is terminated using another command.
V54C365404VD(L) Rev. 0.9 September 2001
6

6 Page



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部品番号部品説明メーカ
V54C365404VD

HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 16M X 4 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 4

Mosel Vitelic  Corp
Mosel Vitelic Corp


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