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V54C3256 の電気的特性と機能

V54C3256のメーカーはMosel Vitelic Corpです、この部品の機能は「256Mbit SDRAM 3.3 VOLT/ TSOP II / SOC BGA / WBGA PACKAGE 16M X 16/ 32M X 8/ 64M X 4」です。


製品の詳細 ( Datasheet PDF )

部品番号 V54C3256
部品説明 256Mbit SDRAM 3.3 VOLT/ TSOP II / SOC BGA / WBGA PACKAGE 16M X 16/ 32M X 8/ 64M X 4
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




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V54C3256 Datasheet, V54C3256 PDF,ピン配置, 機能
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
256Mbit SDRAM
3.3 VOLT, TSOP II / SOC BGA / WBGA
PACKAGE 16M X 16, 32M X 8, 64M X 4
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
4 banks x16Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II, 60 Ball WBGA and
SOC BGA
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Description
The V54C3256(16/80/40)4V(T/S/B) is a four
bank Synchronous DRAM organized as 4 banks x
4Mbit x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit
x 4. The V54C3256(16/80/40)4V(T/S/B) achieves
high speed data transfer rates up to 166 MHz by
employing a chip architecture that prefetches multi-
ple bits and then synchronizes the output data to a
system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T/S/B
6
Access Time (ns)
7PC 7
••
8PC
Power
Std. L
••
Temperature
Mark
Blank
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
1

1 Page





V54C3256 pdf, ピン配列
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
Description Pkg.
TSOP-II
T
Pin Count
54
V 54 C 3 25616 4 V A L T
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
Device
Number
C=CMOS Family
3.3V, LVTTL INTERFACE
16Mx16(8K Refresh)
4 Banks
Special
Feature
Speed
6 ns
7 ns
8 ns
TSOP Component
Package
L=Low Power
Component Rev Level A=0.17um
V=LVTTL
B=0.14um
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
VCC
I/O1
VCCQ
I/O2
I/O3
VSSQ
I/O4
I/O5
VCCQ
I/O6
I/O7
VSSQ
I/O8
VCC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356164V-01
VSS
I/O16
VSSQ
I/O15
I/O14
VCCQ
I/O13
I/O12
VSSQ
I/O11
I/O10
VCCQ
I/O9
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Names
CLK
CKE
CS
RAS
CAS
WE
A0–A12
BA0, BA1
I/O1–I/O16
LDQM, UDQM
VCC
VSS
VCCQ
VSSQ
NC
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
3


3Pages


V54C3256 電子部品, 半導体
MOSEL VITELIC
V54C3256(16/80/40)4V(T/S/B)
V 54 C 3 256XX 4 V B L S
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
Device
Number
C=CMOS Family
3.3V, LVTTL INTERFACE
256Mb(8K Refresh)
4 Banks
Speed
6 ns
Special 7 ns
Feature 8 ns
SOC BGA
Component Package
for 0.14um only
L=Low Power
Component Rev Level A=0.17um
V=LVTTL
B=0.14um
Description Pkg.
SOC BGA
S
Pin Count
60
X16
12
A DQ15 VSS
B DQ14 VSSQ
C VDDQ DQ13
D DQ11 DQ12
E DQ10 VSSQ
F VDDQ DQ9
G NC
DQ8
H NC
VSS
J NC DQMH
K NC
CLK
L A12 CKE
M A11
A9
N A8
A7
P A6
A5
R A4
VSS
X8
12
DQ7 VSS
NC VSSQ
VDDQ DQ6
DQ5
NC
NC VSSQ
VDDQ DQ4
NC NC
NC VSS
NC DQM
NC CLK
A12 CKE
A11 A9
A8 A7
A6 A5
A4 VSS
256 Mb SDRAM Ball Assignment
X4
12
(60-Ball SOC BGA)
PIN A1 INDEX
X4
12
NC VSS
VDD
NC
NC VSSQ
VDDQ NC
VDDQ DQ3
DQ0 VSSQ
NC NC
NC NC
NC VSSQ
VDDQ NC
VDDQ DQ2
DQ1 VSSQ
NC NC
NC NC
NC VSS
VDD
NC
NC DQM
WE# CAS#
NC CLK
RAS# NC
A12 CKE
NC CS#
A11 A9
BA1 BA0
A8 A7
A0 A10
A6 A5
A2 A1
A4 VSS
VDD
A3
TOP VIEW
(See Ball through the Package)
X8
12
VDD DQ0
VDDQ NC
DQ1 VSSQ
NC DQ2
VDDQ NC
DQ3 VSSQ
NC NC
VDD
NC
WE# CAS#
RAS# NC
NC CS#
BA1 BA0
A0 A10
A2 A1
VDD
A3
X16
12
AVDD DQ0
BVDDQ DQ1
CDQ2 VSSQ
DDQ3 DQ4
EVDDQ DQ5
FDQ6 VSSQ
GDQ7
NC
HVDD DQML
JWE# CAS#
KRAS# NC
LNC CS#
MBA1 BA0
NA0 A10
PA2 A1
RVDD
A3
V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002
6

6 Page



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共有リンク

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部品番号部品説明メーカ
V54C3256

256Mbit SDRAM 3.3 VOLT/ TSOP II / SOC BGA / WBGA PACKAGE 16M X 16/ 32M X 8/ 64M X 4

Mosel Vitelic  Corp
Mosel Vitelic Corp
V54C3256164VB

256Mbit SDRAM 3.3 VOLT/ TSOP II / SOC BGA / WBGA PACKAGE 16M X 16/ 32M X 8/ 64M X 4

Mosel Vitelic  Corp
Mosel Vitelic Corp
V54C3256164VBUC

LOW POWER 256Mbit SDRAM 3.3 VOLT/ 54-BALL SOC BGA 54-PIN TSOPII 16M X 16

Mosel Vitelic  Corp
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V54C3256164VBUT

LOW POWER 256Mbit SDRAM 3.3 VOLT/ 54-BALL SOC BGA 54-PIN TSOPII 16M X 16

Mosel Vitelic  Corp
Mosel Vitelic Corp


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