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V54C3128804VTのメーカーはMosel Vitelic Corpです、この部品の機能は「128Mbit SDRAM 3.3 VOLT/ TSOP II / SOC PACKAGE 8M X 16/ 16M X 8/ 32M X 4」です。 |
部品番号 | V54C3128804VT |
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部品説明 | 128Mbit SDRAM 3.3 VOLT/ TSOP II / SOC PACKAGE 8M X 16/ 16M X 8/ 32M X 4 | ||
メーカ | Mosel Vitelic Corp | ||
ロゴ | |||
このページの下部にプレビューとV54C3128804VTダウンロード(pdfファイル)リンクがあります。 Total 30 pages
MOSEL VITELIC
V54C3128(16/80/40)4V(T/S)
128Mbit SDRAM
3.3 VOLT, TSOP II / SOC PACKAGE
8M X 16, 16M X 8, 32M X 4
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
■ 4 banks x 2Mbit x 16 organization
■ 4 banks x 4Mbit x 8 organization
■ 4 banks x 8Mbit x 4 organization
■ High speed data transfer rates up to 166 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 60-ball SOC BGA and 54 Pin
TSOPII
■ LVTTL Interface
■ Single +3.3 V ±0.3 V Power Supply
Description
The V54C3128(16/80/40)4V(T/S) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4V(T/S) achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T/S
•
6
•
Access Time (ns)
7PC 7
••
8PC
•
Power
Std. L
••
Temperature
Mark
Blank
V54C3128(16/80/40)4V(T/S) Rev. 1.2 August 2002
1
1 Page MOSEL VITELIC
V54C3128(16/80/40)4V(T/S)
Description Pkg.
TSOP-II
T
Pin Count
54
V 54 C 3 12816 4 V A L T
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
Device
Number
C=CMOS Family
3.3V, LVTTL INTERFACE
8Mx16(4K Refresh)
4 Banks
Special
Feature
Speed
6 ns
7 ns
8 ns
Component
Package
L=Low Power
Component Rev Level
V=LVTTL
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
VCC
I/O1
VCCQ
I/O2
I/O3
VSSQ
I/O4
I/O5
VCCQ
I/O6
I/O7
VSSQ
I/O8
VCC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 I/O16
52 VSSQ
51 I/O15
50 I/O14
49 VCCQ
48 I/O13
47 I/O12
46 VSSQ
45 I/O11
44 I/O10
43 VCCQ
42 I/O9
41 VSS
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Pin Names
CLK
CKE
CS
RAS
CAS
WE
A0–A11
BA0, BA1
I/O1–I/O16
LDQM, UDQM
VCC
VSS
VCCQ
VSSQ
NC
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V54C3128(16/80/40)4V(T/S) Rev. 1.2 August 2002
3
3Pages MOSEL VITELIC
Capacitance*
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
Symbol Parameter
Max. Unit
CI1 Input Capacitance (A0 to A11)
3.8 pF
CI2 Input Capacitance
3.8 pF
RAS, CAS, WE, CS, CLK, CKE, DQM
CIO
CCLK
Output Capacitance (I/O)
Input Capacitance (CLK)
6 pF
3.5 pF
*Note:Capacitance is sampled and not 100% tested.
V54C3128(16/80/40)4V(T/S)
Absolute Maximum Ratings*
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Block Diagram
x16 Configuration
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 512
x 16 bit
Row decoder
Memory array
Bank 1
4096 x 512
x16 bit
Row decoder
Memory array
Bank 2
4096 x 512
x 16 bit
Row decoder
Memory array
Bank 3
4096 x 512
x 16 bit
Input buffer Output buffer
I/O1-I/O16
Control logic & timing generator
V54C3128(16/80/40)4V(T/S) Rev. 1.2 August 2002
6
6 Page | |||
ページ | 合計 : 30 ページ | ||
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PDF ダウンロード | [ V54C3128804VT データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
V54C3128804VBGA | 128Mbit SDRAM 3.3 VOLT/ BGA PACKAGE | Mosel Vitelic Corp |
V54C3128804VE | (V54C3xxxx4VE) 64Mbit SDRAM | ProMOS Technologies |
V54C3128804VS | 128Mbit SDRAM 3.3 VOLT/ TSOP II / SOC PACKAGE 8M X 16/ 16M X 8/ 32M X 4 | Mosel Vitelic Corp |
V54C3128804VT | 128Mbit SDRAM 3.3 VOLT/ TSOP II / SOC PACKAGE 8M X 16/ 16M X 8/ 32M X 4 | Mosel Vitelic Corp |