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V54C3128404VBGAのメーカーはMosel Vitelic Corpです、この部品の機能は「128Mbit SDRAM 3.3 VOLT/ BGA PACKAGE」です。 |
部品番号 | V54C3128404VBGA |
| |
部品説明 | 128Mbit SDRAM 3.3 VOLT/ BGA PACKAGE | ||
メーカ | Mosel Vitelic Corp | ||
ロゴ | |||
このページの下部にプレビューとV54C3128404VBGAダウンロード(pdfファイル)リンクがあります。 Total 30 pages
MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
128Mbit SDRAM
3.3 VOLT, BGA PACKAGE
8M X 16
16M X 8
32M X 4
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Access Time (tAC3) CAS Latency = 3
Clock Access Time (tAC2) CAS Latency = 2
6
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
PRELIMINARY
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
s 4 banks x 2Mbit x 16 organization
s 4 banks x 4Mbit x 8 organization
s 4 banks x 8Mbit x 4 organization
s High speed data transfer rates up to 166 MHz
s Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s Single Pulsed RAS Interface
s Data Mask for Read/Write Control
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 2, 3
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
s Multiple Burst Read with Single Write Operation
s Automatic and Controlled Precharge Command
s Random Column Address every CLK (1-N Rule)
s Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 60 Pin WBGA
s LVTTL Interface
s Single +3.3 V ±0.3 V Power Supply
Description
The V54C3128(16/80/40)4V(BGA) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4V(BGA) achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
B
•
6
•
Access Time (ns)
7PC 7
••
8PC
•
Power
Std. L
••
Temperature
Mark
Blank
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
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1 Page MOSEL VITELIC
Capacitance*
TA = 0 to 70°C, VCC = 3.3 V ± 0.3 V, f = 1 Mhz
Symbol Parameter
Max. Unit
CI1 Input Capacitance (A0 to A11)
3.8 pF
CI2 Input Capacitance
3.8 pF
RAS, CAS, WE, CS, CLK, CKE, DQM
CIO
CCLK
Output Capacitance (I/O)
Input Capacitance (CLK)
6 pF
3.5 pF
*Note:Capacitance is sampled and not 100% tested.
V54C3128(16/80/40)4V(BGA)
Absolute Maximum Ratings*
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Block Diagram
x16 Configuration
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
4096 x 512
x 16 bit
Row decoder
Memory array
Bank 1
4096 x 512
x16 bit
Row decoder
Memory array
Bank 2
4096 x 512
x 16 bit
Row decoder
Memory array
Bank 3
4096 x 512
x 16 bit
Input buffer Output buffer
I/O1-I/O16
Control logic & timing generator
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
3
3Pages MOSEL VITELIC
V54C3128(16/80/40)4V(BGA)
Signal Pin Description
Pin Type
CLK
Input
CKE
Input
CS Input
RAS, CAS Input
WE
A0 - A11 Input
Signal Polarity
Function
Pulse
Positive The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
Edge clock.
Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Level
— During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
• 32M x 4 SDRAM CA0–CA9, CA11.
• 16M x 8 SDRAM CA0–CA9.
• 8M x 16 SDRAM CA0–CA8.
BA0,
BA1
DQx
LDQM
UDQM
Input
Input
Output
Input
VCC, VSS Supply
VCCQ
VSSQ
Supply
Level
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
— Selects which bank is to be active.
Level
— Data Input/Output pins operate in the same manner as on conventional DRAMs.
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
Power and ground for the input buffers and the core logic.
— — Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
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部品番号 | 部品説明 | メーカ |
V54C3128404VBGA | 128Mbit SDRAM 3.3 VOLT/ BGA PACKAGE | Mosel Vitelic Corp |