DataSheet.jp

V53C8128H の電気的特性と機能

V53C8128HのメーカーはMosel Vitelic Corpです、この部品の機能は「ULTRA-HIGH PERFORMANCE/ 128K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 V53C8128H
部品説明 ULTRA-HIGH PERFORMANCE/ 128K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




このページの下部にプレビューとV53C8128Hダウンロード(pdfファイル)リンクがあります。

Total 20 pages

No Preview Available !

V53C8128H Datasheet, V53C8128H PDF,ピン配置, 機能
MOSEL-VITELIC
V53C8128H
ULTRA-HIGH PERFORMANCE,
128K X 8 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Fast Page Mode With EDO Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
PREVL5I3MCIN81A2R8YH
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
Features
s 128K x 8-bit organization
s RAS access time: 35, 40, 45, 50 ns
s EDO Page Mode supports sustained I/O data
rates up to 71.5 MHz
s Low power dissipation
• V53C8128H-50
— Operating Current – 135 mA max
— TTL Standby Current – 2.0 mA max
s Low CMOS Standby Current
• V53C8128H – 1.0 mA max
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s Refresh Interval
• V53C8128H – 512 cycles/8 ms
s Available in 26/24 pin 300 mil SOJ package
Description
The V53C8128H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8128H offers a combination of features: EDO
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with extended data out operation allows random
access of up to 256 columns (x8) bits within a row
with cycle times as short as 14 ns. Because of static
circuitry, the CAS clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements for fast usable speed.
These features make the V53C8128H ideally suited
for graphics, digital signal processing and high
performance Peripherals.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
Package Outline
K
Access Time (ns)
35 40 45
•••
50
V53C8128H Rev. 1.1 November 1997
1
Power
Std.
Temperature
Mark
Blank

1 Page





V53C8128H pdf, ピン配列
MOSEL-VITELIC
Block Diagram
OE
WE
CAS
RAS RAS CLOCK
GENERATOR
128K x 8
V53C8128H
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
REFRESH
COUNTER
9
A0
A1
A7
A8
Y0–Y7
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
256 x 8
I/O
BUFFER
I/O 1
I/O2
I/O3
I/O4
I/O 5
I/O6
I/O7
I/O8
X0–X8
512
MEMORY
ARRAY
3838 03
V53C8128H Rev. 1.1 November 1997
3


3Pages


V53C8128H 電子部品, 半導体
MOSEL-VITELIC
AC Characteristics (continued)
JEDEC
# Symbol Symbol Parameter
27 tWL1CL2
28 tCL1WH1
29 tWL1WH1
30 tRL1WH1
tWCS
tWCH
tWP
tWCR
31 tWL1RH1 tRWL
32 tDVWL2
33 tWL1DX
34 tWL1GL2
35 tGH2DX
36 tRL2RL2
(RMW)
37 tRL1RH1
(RMW)
38 tCL1WL2
39 tRL1WL2
tDS
tDH
tWOH
tOED
tRWC
tRRW
tCWD
tRWD
40 tCL1CH1
41 tAVWL2
42 tCL2CL2
tCRW
tAWD
tPC
43 tCH2CL2
44 tAVRH1
tCP
tCAR
45 tCH2QV
tCAP
46 tRL1DX
tDHR
47 tCL1RL2 tCSR
48 tRH2CL2
49 tRL1CH1
tRPC
tCHR
50 tCL2CL2
(RMW)
tPCM
Write Command Setup Time
Write Command Hold Time
Write Pulse Width
Write Command Hold Time
from RAS
Write Command to RAS
Lead Time
Data in Setup Time
Data in Hold Time
Write to OE Hold Time
OE to Data Delay Time
Read-Modify-Write
Cycle Time
Read-Modify-Write Cycle
RAS Pulse Width
CAS to WE Delay
RAS to WE Delay in
Read-Modify-Write Cycle
CAS Pulse Width (RMW)
Col. Address to WE Delay
EDO Page Mode
Read or Write Cycle Time
CAS Precharge Time
Column Address to RAS
Setup Time
Access Time from
Column Precharge
Data in Hold Time
Referenced to RAS
CAS Setup Time
CAS-before-RAS Refresh
RAS to CAS Precharge Time
CAS Hold Time
CAS-before-RAS Refresh
EDO Page Mode Read-
Modify-Write Cycle Time
V53C8128H
35 40 45 50
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Notes
0 0 0 0 ns 12, 13
5 5 6 7 ns
5567
28 30 35 40
ns
ns
12 12 13 14
ns
0000
4567
5678
5678
105 110 115 130
ns 14
ns 14
ns 14
ns 14
ns
70 75 80 87
ns
28 30 32 34
54 58 62 68
ns 12
ns 12
46 48 50 52
35 38 41 42
14 15 17 19
ns
ns 12
ns
4567
18 20 22 24
ns
ns
21
23
25
27 ns
7
28 30 35 40
ns
10 10 10 10
ns
0 0 0 0 ns
8 8 10 12 ns
58 60 65 70
ns
V53C8128H Rev. 1.1 November 1997
6

6 Page



ページ 合計 : 20 ページ
 
PDF
ダウンロード
[ V53C8128H データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
V53C8128H

ULTRA-HIGH PERFORMANCE/ 128K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM

Mosel Vitelic  Corp
Mosel Vitelic Corp


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap