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V53C16256H の電気的特性と機能

V53C16256HのメーカーはMosel Vitelic Corpです、この部品の機能は「256K x 16 FAST PAGE MODE CMOS DYNAMIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 V53C16256H
部品説明 256K x 16 FAST PAGE MODE CMOS DYNAMIC RAM
メーカ Mosel Vitelic Corp
ロゴ Mosel Vitelic  Corp ロゴ 




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V53C16256H Datasheet, V53C16256H PDF,ピン配置, 機能
MOSEL VITELIC
V53C16256H
256K x 16 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Fast Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
30
30 ns
16 ns
19 ns
65 ns
35
35 ns
18 ns
21 ns
70 ns
40
40 ns
20 ns
23 ns
75 ns
45
45 ns
22 ns
25 ns
80 ns
50
50 ns
24 ns
28 ns
90 ns
60
60 ns
30 ns
35 ns
110 ns
Features
s 256K x 16-bit organization
s Fast Page Mode for a sustained data rate
of 53 MHz.
s RAS access time: 30, 35, 40, 45, 50, 60 ns
s Dual CAS Inputs
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s Refresh Interval: 512 cycles/8 ms
s Available in 40-pin 400 mil SOJ and
40/44L-pin 400 mil TSOP-II packages
s Single +5V ±10% Power Supply
s TTL Interface
Description
The V53C16256H is a 262,144 x 16 bit high-
performance CMOS dynamic random access mem-
ory. The V53C16256H offers Fast Page mode with
dual CAS inputs. An address, CAS and RAS input
capacitances are reduced to one quarter when the
x4 DRAM is used to construct the same memory
density. The V53C16256H has symmetric address
and accepts 512 cycle 8ms interval.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 19ns.
The V53C16256H is best suited for graphics, and
DSP applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
-40°C to +85°C
Package Outline
KT
••
••
30
Access Time (ns)
35 40 45 50
••••
••••
Power
Temperature
60 Std.
Mark
• • Blank
••
I
V53C16256H Rev. 2.3 June 1998
1

1 Page





V53C16256H pdf, ピン配列
MOSEL VITELIC
V53C16256H
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ................................ –10°C to +80°C
Storage Temperature (plastic) ..... –55°C to +125°C
Voltage Relative to VSS ..................–1.0 V to +7.0V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
TA = 25°C, VCC = 5V ± 10%, VSS = 0 V
Symbol Parameter
Typ. Max.
CIN1
CIN2
Address Input
RAS, UCAS, LCAS,
WE, OE
34
45
COUT
Data Input/Output
57
* Note: Capacitance is sampled and not 100% tested
Unit
pF
pF
pF
Block Diagram
OE
WE
UCAS
LCAS
RAS
RAS CLOCK
GENERATOR
256K x 16
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
REFRESH
COUNTER
9
A0
A1
A7
A8
Y0 -Y 8
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
512 x 16
X0 -X8
512
MEMORY
ARRAY
I/O
BUFFER
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
16256H-04
V53C16256H Rev. 2.3 June 1998
3


3Pages


V53C16256H 電子部品, 半導体
MOSEL VITELIC
V53C16256H
AC Characteristics (Cont’d)
JEDEC
# Symbol Symbol Parameter
30 35 40 45 50 60
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
21 tCL1QX
tLZ
OE or CAS to
0
0
0
0
0
0 ns 16
Low-Z Output
22 tCH2QZ
tHZ
OE or CAS to
High-Z Output
0 5 0 6 0 6 0 7 0 8 0 10 ns 16
23 tRL1AX
tAR
Column Address 26
28
30
35
40
50
ns
Hold Time
from RAS
24 tRL1AV
tRAD RAS to Column
Address Delay
Time
10 14 11 17 12 20 13 23 14 26 15 30 ns 11
25 tCL1RH1(W) tRSH (W) RAS or CAS Hold 10 10 12 13 14 15 ns
Time in Write Cycle
26 tWL1CH1
tCWL
Write Command to 10
11
12
13
14
15
ns
CAS Lead Time
27 tWL1CL2
tWCS
Write Command
0
0
0
0
0
0 ns 12, 13
Setup Time
28 tCL1WH1 tWCH Write Command
5
5
5
6
7 10 ns
Hold Time
29 tWL1WH1 tWP
Write Pulse Width 5
5
5
6
7 10 ns
30 tRL1WH1 tWCR Write Command
26
28
30
35
40
50
ns
Hold Time from
RAS
31 tWL1RH1
tRWL
Write Command to 10
11
12
13
14
15
ns
RAS Lead Time
32 tDVWL2
tDS
Data in Setup Time 0
0
0
0
0
0 ns 14
33 tWL1DX
tDH
Data in Hold Time 5
5
5
6
7 10 ns 14
34 tWL1GL2 tWOH Write to OE Hold
5
5
6
7
8 10 ns 14
Time
35 tGH2DX
tOED
OE to Data Delay 5
5
6
7
8 10 ns 14
Time
36 tRL2RL2
tRWC
Read-Modify-Write 100
105
110
115
130 170
ns
(RMW)
Cycle Time
37 tRL1RH1 tRRW Read-Modify-Write 65 70 75 80 87 105 ns
(RMW)
Cycle RAS Pulse
Width
38 tCL1WL2 tCWD CAS to WE Delay 26 28 30 32 34 40 ns 12
39 tRL1WL2 tRWD RAS to WE Delay 50 54 58 62 68 85 ns 12
in Read-Modify-
Write Cycle
40 tCL1CH1 tCRW CAS Pulse Width 44 46 48 50 52 65 ns
(RMW)
V53C16256H Rev. 2.3 June 1998
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
V53C16256

256K x 16 FAST PAGE MODE CMOS DYNAMIC RAM

Mosel Vitelic  Corp
Mosel Vitelic Corp
V53C16256H

256K x 16 FAST PAGE MODE CMOS DYNAMIC RAM

Mosel Vitelic  Corp
Mosel Vitelic Corp
V53C16256SH

256K X 16 FAST PAGE MODE CMOS DYNAMIC RAM WITH SELF REFRESH

Mosel Vitelic  Corp
Mosel Vitelic Corp


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