PDF V437464S24V Data sheet ( Hoja de datos )

Número de pieza	V437464S24V
Descripción	3.3 VOLT 64M x 72 HIGH PERFORMANCE UNBUFFERED ECC SDRAM MODULE
Fabricantes	Mosel Vitelic Corp
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No Preview Available ! MOSEL VITELIC V437464S24V 3.3 VOLT 64M x 72 HIGH PERFORMANCE UNBUFFERED ECC SDRAM MODULE PRELIMINARY Features s 168 Pin Unbuffered ECC 67,108,864 x 72 bit Oganization SDRAM Modules s Utilizes High Performance 32M x 8 SDRAM in TSOPII-54 Packages s Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification s Single +3.3V (± 0.3V) Power Supply s Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) s Auto Refresh (CBR) and Self Refresh s All Inputs, Outputs are LVTTL Compatible s 8192 Refresh Cycles every 64 ms s Serial Present Detect (SPD) s Description The V437464S24V memory module is organized 67,108,864 x 72 bits in a 168 pin dual in line memory module (DIMM). The 64M x 72 unbuffered DIMM uses 18 Mosel-Vitelic 32M x 8 ECC SDRAM. The x72 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Part Number Speed Grade Configuration V437464S24VXTG-75PC -75PC, CL=2,3 (133 MHz) 64M x 72 V437464S24VXTG-75 -75, CL=3 (133 MHz) 64M x 72 V437464S24VXTG-10PC -10PC, CL=2,3 (100 MHz) 64M x 72 V437464S24V Rev. 1.0 January 2002 1 1 page MOSEL VITELIC V437464S24V SPD-Table : (Continued) Byte Num- ber Function Described 28 Minimum Row Active to Row Active Delay tRRD 29 Minimum RAS to CAS Delay tRCD 30 Minimum RAS Pulse Width tRAS 31 Module Bank Density (Per Bank) 32 SDRAM Input Setup Time 33 SDRAM Input Hold Time 34 SDRAM Data Input Setup Time 35 SDRAM Data Input Hold Time 62-61 Superset Information (May be used in Fu- ture) 62 SPD Revision 63 Checksum for Bytes 0 - 62 64 Manufacturer’s JEDEC ID Code 65-71 Manufacturer’s JEDEC ID Code (cont.) 72 Manufacturing Location 73-90 Module Part Number (ASCII) 91-92 PCB Identification Code 93 Assembly Manufacturing Date (Year) 94 Assembly Manufacturing Date (Week) 95-98 Assembly Serial Number 99-125 Reserved 126 Intel Specification for Frequency 127 Reserved 128+ Unused Storage Location SPD Entry Value 14 ns/15 ns/16 ns 15 ns/20 ns 42 ns/45 ns 256 MByte 1.5 ns/2.0 ns 0.8 ns/1.0 ns 1.5 ns/2.0 ns 0.8 ns/1.0 ns Revision 2/1.2 Mosel Vitelic V437464S24V DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Symbol Parameter VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage (IOUT = –4.0 mA) -75PC 0E Hex Value -75 0F 0F 14 2A 2D 40 40 15 15 08 08 15 15 08 08 00 00 02 02 10 8C 40 40 00 00 00 00 64 64 00 00 00 00 Limit Values Min. Max. 2.0 –0.5 VCC+0.3 0.8 2.4 — -10PC 10 14 2D 40 20 10 20 10 00 12 C3 40 00 00 64 00 00 Unit V V V V437464S24V Rev. 1.0 January 2002 5 5 Page MOSEL VITELIC Label Information Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) DIMM manufacture date code V437464S24V Module Density MOSEL VITELIC V437464S24VXXX-XX 512MB CLX PC133U-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan CAS Latency 2=CL2 3=CL3 PC133 U -XXX 54 2 A UNBUFFERED DIMM CL= 3 or 2 (CLK) tRCD= 3 or 2 (CLK) tRP= 3 or 2 (CLK) Gerber file Intel PC100 x8 Based JEDEC SPD Revision 2 tAC = 5.4 ns V437464S24V Rev. 1.0 January 2002 11 11 Page

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