PDF V4374128C24VXXG-75PC Data sheet ( Hoja de datos )

Número de pieza	V4374128C24VXXG-75PC
Descripción	1GB 168-PIN REGISTERED PLL ECC SDRAM DIMM 3.3 VOLT 128M x 72
Fabricantes	Mosel Vitelic Corp
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No Preview Available ! MOSEL VITELIC V4374128C24V 1GB 168-PIN REGISTERED PLL ECC SDRAM DIMM 3.3 VOLT 128M x 72 PRELIMINARY Features s 168 Pin Registered ECC 134,217,728 x 72 bit Oganization SDRAM Modules s Utilizes High Performance 64M x 4 SDRAM in SOC Packages s Fully PC Board Layout Compatible to INTEL’S Rev 1.2 Module Specification s Single +3.3V (± 0.3V) Power Supply s Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) s Auto Refresh (CBR) and Self Refresh s All Inputs, Outputs are LVTTL Compatible s 8192 Refresh Cycles every 64 ms s Serial Presence Detect (SPD) s Part Number Speed Grade Configuration V4374128C24VXXG-75PC -75PC, CL=2,3 (133 MHz) 128M x 72 V4374128C24VXXG-75 -75, CL=3 (133 MHz) 128M x 72 V4374128C24VXXG-10PC -10PC, CL=2,3 (100 MHz) 128M x 72 Description The V4374128C24V memory module is organized 134,217,728 x 72 bits in a 168 pin dual in line memory module (DIMM). The 128M x 72 registered DIMM uses 36 Mosel-Vitelic 64M x 4 ECC SDRAM. The x72 registered modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. V4374128C24V Rev. 1.1 January 2002 1 1 page MOSEL VITELIC V4374128C24V Serial Presence Detect Information A serial presence detect storage device – E2PROM – is assembled onto the module. Informa- tion about the module configuration, speed, etc. is SPD-Table: written into the E2PROM device during module pro- duction using a serial presence detect protocol (I2C synchronous 2-wire bus) Byte Num- ber Function Described SPD Entry Value 0 Number of SPD bytes 128 1 Total bytes in Serial PD 256 2 Memory Type SDRAM 3 Number of Row Addresses (without BS bits) 13 4 Number of Column Addresses (for x8 SDRAM) 11 5 Number of DIMM Banks 2 6 Module Data Width 72 7 Module Data Width (continued) 0 8 Module Interface Levels LVTTL 9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 11 Dimm Config (Error Det/Corr.) ECC 12 Refresh Rate/Type Self-Refresh, 7.8µs 13 SDRAM width, Primary x4 14 Error Checking SDRAM Data Width n/a / x4 15 Minimum Clock Delay from Back to Back Random Column Address tccd = 1 CLK 16 Burst Length Supported 1, 2, 4, 8 17 Number of SDRAM Banks 4 18 Supported CAS Latencies CL =2, 3 19 CS Latencies CS Latency = 0 20 WE Latencies WL = 0 21 SDRAM DIMM Module Attributes Registered/Buffered 22 SDRAM Device Attributes: General Vcc tol ± 10% 23 Minimum Clock Cycle Time at CAS Latency 7.5 ns/10.0 ns =2 24 Maximum Data Access Time from Clock for 5.4 ns/6.0 ns CL = 2 25 Minimum Clock Cycle Time at CL = 1 Not Supported 26 Maximum Data Access Time from Clock at Not Supported CL = 1 27 Minimum Row Precharge Time 15 ns/20 ns -75PC 80 08 04 0D 0B Hex Value -75 80 08 04 0D 0B -10PC 80 08 04 0D 0B 02 02 02 48 48 48 00 00 00 01 01 01 75 75 A0 54 54 60 02 02 02 82 82 82 04 04 04 04 04 04 01 01 01 0F 0F 0F 04 04 04 06 06 06 01 01 01 01 01 01 1F 1F 1F 0E 0E 0E 75 A0 A0 54 60 60 00 00 00 00 00 00 0F 14 14 V4374128C24V Rev. 1.1 January 2002 5 5 Page MOSEL VITELIC Package Diagram SDRAM DIMM Module Package FRONT VIEW 5.256 (133.50) 5.244 (133.20) V4374128C24V .157 (3.99) MAX .079 (2.00) R (2X) .118 (3.00) R (2X) .118 (3.00) TYP. .118 (3.00) TYP. .250 (6.35) TYP. PIN 1 .039 (1.00) R(2X) .040 (1.02) 4.550 (115.57) TYP. .050 (1.27) TYP. 1.705 (43.31) 1.695 (43.05) .700 (17.78) TYP. PIN 84 .054 (1.37) .046 (1.17) BACK VIEW PIN 168 NOTE: All dimensions in inches (millimeters) MAX MIN or typical where noted. 1.661 (42.18) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) PIN 85 V4374128C24V Rev. 1.1 January 2002 11 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
V4374128C24VXXG-75PC	1GB 168-PIN REGISTERED PLL ECC SDRAM DIMM 3.3 VOLT 128M x 72	Mosel Vitelic Corp

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