PDF V436664X24V Data sheet ( Hoja de datos )

Número de pieza	V436664X24V
Descripción	512MB 144-PIN UNBUFFERED SDRAM SODIMM/ 64M X 64 3.3VOLT
Fabricantes	Mosel Vitelic Corp
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No Preview Available ! MOSEL VITELIC V436664X24V 512MB 144-PIN UNBUFFERED SDRAM SODIMM, 64M X 64 3.3VOLT PRELIMINARY Features s JEDEC-standard 144 pin, Small-Outline, Dual in line Memory Module (SODIMM) s Serial Presence Detect with E2PROM s Nonbuffered s Fully Synchronous, All Signals Registered on Positive Edge of System Clock s Single +3.3V (± 0.3V) Power Supply s All Device Pins are LVTTL Compatible s 8192 Refresh Cycles every 64 ms s Self-Refresh Mode s Internal Pipelined Operation; Column Address can be changed every System Clock s Programmable Burst Lengths: 1, 2, 4, 8 s Auto Precharge and Piecharge all Banks by A10 s Data Mask Function by DQM s Mode Register Set Programming s Programmable (CAS Latency: 2, 3 Clocks) s SOC component package Description The V436664X24V memory module is organized 67,108,864x 64 bits in a 144 pin SODIMM. The 64M x 64 memory module uses 16 Mosel-Vitelic 64M x 4 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Part Number Speed Grade Configuration V436664X24VXXX-75PC -75PC, CL=2,3 (133 MHz) 64M x 64 V436664X24VXXX-75 -75, CL=3 (133 MHz) 64M x 64 V436664X24VXXX-10PC -10PC, CL=2,3 (100 MHz) 64M x 64 32M x 8 32M x 8 32M x 8 32M x 8 1 59 61 Pin 2 on Backside 143 Pin 144 on Backside V436664X24V Rev.1.0 January 2002 1 1 page MOSEL VITELIC V436664X24V Block Diagram Serial Presence Detect Information A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the SPD-Table for modules: E2PROM device during module production using a se- rial presence detect protocol (I2C synchronous 2-wire bus) Byte Num- ber Function Described SPD Entry Value 0 Number of SPD bytes 128 1 Total bytes in Serial PD 256 2 Memory Type SDRAM 3 Number of Row Addresses (without BS bits) 13 4 Number of Column Addresses ( x8 SDRAM) 11 5 Number of DIMM Banks 1 6 Module Data Width 64 7 Module Data Width (continued) 0 8 Module Interface Levels LVTTL 9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0ns 11 Dimm Config (Error Det/Corr.) none 12 Refresh Rate/Type Self-Refresh,15.6 µs 13 SDRAM width, Primary x4 14 Error Checking SDRAM Data Width n/a / 15 Minimum Clock Delay from Back to Back Ran- dom Column Address tccd = 1 CLK 16 Burst Length Supported 1, 2, 4 & 8 17 Number of SDRAM Banks 4 18 Supported CAS Latencies CL = 2 / 3 19 CS Latencies CS Latency = 0 20 WE Latencies WL = 0 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 22 SDRAM Device Attributes: General Vcc tol ± 10% 23 Minimum Clock Cycle Time at CAS Latency = 2 7.5 ns/10.0 ns -75PC 80 08 04 0D 0B 01 40 00 01 75 54 00 80 04 00 01 0F 04 06 01 01 00 0E 75 Hex Value -75 80 08 04 0D 0B 01 40 00 01 75 54 00 80 04 00 01 0F 04 06 01 01 00 0E A0 -10PC 80 08 04 0D 0B 01 40 00 01 A0 60 00 80 04 00 01 0F 04 06 01 01 00 0E A0 24 Maximum Data Access Time from Clock for CL =2 5.4ns/6.0ns 54 60 60 25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00 26 Maximum Data Access Time from Clock at CL = Not Supported 00 00 00 1 27 Minimum Row Precharge Time 15 ns / 20 ns 0F 14 14 V436664X24V Rev. 1.0 January 2002 5 5 Page MOSEL VITELIC Package Diagram V436664X24V 144 Pin SODIMM SOC component package 1 59 61 Pin 2 on Backside 3.3V 2.661 NOTE: 1. All dimensions in inches. Tolerances ±0.005 unless otherwise specified. 0.039 1.25 0.787 143 Pin 144 on Backside 00..114107 V436664X24V Rev. 1.0 January 2002 11 11 Page

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