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PDF V436616Y24VXXG-75PC Data sheet ( Hoja de datos )
| Número de pieza | V436616Y24VXXG-75PC | |
| Descripción | 3.3 VOLT 16M x 64 HIGH PERFORMANCE SDRAM UNBUFFERED SODIMM | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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MOSEL VITELIC
V436616Y24V
3.3 VOLT 16M x 64 HIGH PERFORMANCE
SDRAM UNBUFFERED SODIMM
PRELIMINARY
Features
s JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
s Serial Presence Detect with E2PROM
s Nonbuffered
s Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
s Single +3.3V (± 0.3V) Power Supply
s All Device Pins are LVTTL Compatible
s 8192 Refresh Cycles every 64 ms
s Self-Refresh Mode
s Internal Pipelined Operation; Column Address
can be changed every System Clock
s Auto Precharge and Piecharge all Banks by A10
s Data Mask Function by DQM
s Mode Register Set Programming
s Programmable (CAS Latency:2, 3 Clocks)
Description
The V436616Y24V memory module is organized
16,777,216 x 64 bits in a 144 pin SODIMM. The
16M x 64 memory module uses 4 Mosel-Vitelic 16M
x 16 SDRAM. The x64 modules are ideal for use in
high performance computer systems where
increased memory density and fast access times
are required.
Part Number
Speed
Grade
Configuration
V436616Y24VXXG-75PC 133MHz CL2,3
16M x 64
V436616Y24VXXG-75
133MHz CL3
16M x 64
V436616Y24VXXG-10PC 100MHz CL2,3
16M x 64
4M x 16
1 59 61
Pin 2 on Backside
4M x 16
143
Pin 144 on Backside
V436616Y24V Rev. 1.0 January 2002
1
1 page  
MOSEL VITELIC
V436616Y24V
SPD-Table for modules: (Continued)
Byte Num-
ber Function Described
SPD Entry Value
28 Minimum Row Active to Row Active Delay
tRRD
29 Minimum RAS to CAS Delay tRCD
30 Minimum RAS Pulse Width tRAS
31 Module Bank Density (Per Bank)
14 ns/15 ns/16 ns
15 ns/20 ns
42 ns/45 ns
128 Mbyte
32 SDRAM Input Setup Time
1.5 ns
33 SDRAM Input Hold Time
0.8 ns
34 SDRAM Data Input Setup Time
1.5 ns
35 SDRAM Data Input Hold Time
0.8 ns
36-61
Superset Information (May be used in Future)
62 SPD Revision
Revision 2
63 Checksum for Bytes 0 - 62
64 Manufacturer’s JEDEC ID Code
Mosel Vitelic
65-71
Manufacturer’s JEDEC ID Code (cont.)
72 Manufacturing Location
1 = US, 2 = Taiwan
73-90
Module Part Number (ASCII)
V436616Y24V
91-92
PCB Identification Code
Current PCB Revision
93 Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
94 Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
95-98
Assembly Serial Number
byte 95 = LSB, byte 98 =
MSB
99-125 Reserved
126 Intel Specification for Frequency
127 Supported frequency
128+
Unused Storage Location
-75PC
0E
0F
2A
20
15
08
15
08
00
02
E4
40
00
00
64
00
Hex Value
-75
0F
14
2D
20
15
08
15
08
00
02
29
40
00
00
64
00
-10PC
10
14
30
20
20
10
20
10
00
12
9A
40
00
00
64
00
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Symbol Parameter
VIH
VIL
VOH
VOL
Input High Voltage
Input Low Voltage
Output High Voltage (IOUT = –4.0 mA)
Output Low Voltage (IOUT = 4.0 mA)
Limit Values
Min.
Max.
2.0
–0.5
VCC+0.3
0.8
2.4 —
— 0.4
Unit
V
V
V
V
V436616Y24V Rev. 1.0 January 2002
5
5 Page 
MOSEL VITELIC
Module Label Information
Part Number
Criteria of PC100 or PC133
(refer to MVI datasheet)
DIMM manufacture date code
V436616Y24V
Module Density
MOSEL VITELIC
V436616Y24XXX-XX 128MB CLX
PC133U-XXX-542-A
XXXX-XXXXXXX
Assembly in Taiwan
CAS Latency
2=CL2
3=CL3
PC133 U -XXX 54 2 A
UNBUFFERED DIMM
CL= 3 or 2 (CLK)
tRCD= 3 or 2 (CLK)
tRP= 3 or 2 (CLK)
Gerber file Intel PC100 x16 Based
JEDEC SPD Revision 2
tAC = 5.4 ns
V436616Y24V Rev. 1.0 January 2002
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet V436616Y24VXXG-75PC.PDF ] | |
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