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V320 の電気的特性と機能

V320のメーカーはFairchild Semiconductorです、この部品の機能は「V320 8-Bit Registered Bus Transceiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 V320
部品説明 V320 8-Bit Registered Bus Transceiver
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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V320 Datasheet, V320 PDF,ピン配置, 機能
April 1998
Revised October 1998
V320
8-Bit Registered Bus Transceiver
General Description
The V320 is an 8-bit universal bus transceiver designed for
high speed interfacing with the VME320 backplane. It has
output characteristics optimized for driving large capacitive
loads and features modified input levels (VIH/VIL) for
increased noise immunity and reduced input skew. The
V320 functionality consists of bus transceiver circuits with
3-STATE, D-type flip-flops, and control circuitry arranged
for multiplexed transmission of data directly from the input
bus or from the internal registers. Data on the A or B bus
will be clocked into the registers as the appropriate clock
pin goes to a high logic level. OE and direction pins are
provided to control the transceiver function. In the trans-
ceiver mode, data present at the high impedance port may
be stored in either the A or B register or in both. The select
controls can multiplex stored and real time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is active
LOW. In the isolation mode (OE HIGH) A data may be
stored in the B register and/or B data may be stored in the
A register.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s Guaranteed output skew
s Guaranteed MOS (Multiple Output Switching) Specifica-
tions
s Output switching specified for both 50 pF and 250 pF,
and 500 pF loads
s Guaranteed simultaneous switching noise level (VOLP/
VOLV) and dynamic threshold performance (VIHD/VILD)
s Glitch free power up/down high impedance for live inser-
tion
s BiCMOS technology for high drive and low power dissi-
pation
s 40°C to 85°C commercial temperature and VCC specifi-
cations
s Modified specifications across VCC and temperature
(VCC = 5.0V ±1%, T = 25°C ± 20°C) present more realis-
tic system conditions
s Available in TSSOP (MTC)
Ordering Code:
Order Number Package Number
Package Description
V320MTC
MTC24
24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
D Direction A-to-B (High) B-to A (Low)
OE Output Enable (Active LOW)
CLKAB/SELAB A-to-B Clock/Select
CLKBA/SELBA B-to-A Clock/Select
A0–7
A Inputs/Outputs (TTL)
B0–7
B Inputs/Outputs (TTL)
© 1998 Fairchild Semiconductor Corporation DS500149.prf
www.fairchildsemi.com

1 Page





V320 pdf, ピン配列
Absolute Maximum Ratings(Note 1)
DC Input Voltage (VI)
DC Output Voltage (VO)
Outputs 3-STATE
Outputs Active (Note 2)
DC Output Sink Current into
A-port/B-port IOL
DC Output Source Current from
A-port/B-port IOH
DC Input Diode Current (IIK)
VI < 0V
ESD Rating typical
Storage temperature (TSTG)
Max IOL (Current Applied to a
LOW Output)
0.5V to +7.0V
0.5V to +7.0V
0.5V to VCC +0.5V
64 mA
32 mA
30 mA to +5.0 mA
> 2000V
65° C to +15°C
2 X IOL Spec.
Recommended Operating
Conditions
Supply Voltage VCC
Operating VCC
Minimum Input Edge Rate
4.5V to 5.5V
Data Input
50 mV/ns
Enable
20 mV/ns
Clock
100 mV/ns
Operating Temperature (TA)
40°C to +85°C
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics (4.5V < VCC 5.5V)
Over Recommended Operating Free-Air Temperature Range (Unless Otherwise Noted)
Symbol
Parameter
VCC
(V)
Min
Typ
Max
VIH B-Port/A-Port HIGH Level Input Voltage
4.5–5.5
4.95–5.05
2.0
1.8
(Note 3)
VIL B-Port/A-Port LOW Level Input Voltage
4.5–5.5
4.95–5.05
0.8
1.2
(Note 3)
VOH B-Port/A-Port HIGH Level Output Voltage
4.5 2.5
4.5 2.0
IOH B-Port/A-Port High Level Output Current Drive
VOL B-Port/A-Port LOW Level Output Voltage
IOL B-Port/A-Port Low Level Output Current Drive
(Sink)
4.5 32
4.5 0.55
4.5 64
IOS B-Port/A-Port Short Circuit Current
IOFF A-Port and Power-OFF Leakage Current
Control Pins
5.5 100
0.0
275
100uA
ICCH B-Port/A-Port Quiescent Power Supply Current
5.5
ICCI B-Port/A-Port B-Port/A-Port
5.5
ICCZ B-Port/A-Port 3-STATE Power Supply Current
5.5
Note 3: Extended Characteristics (4.95 > VCC > 5.05, T = 25°C ± 20°C)
250
30
50
Units
Conditions
V Recognized HIGH Signal
V Recognized LOW Signal
V 3 mA
32 mA
mA VOH = 2.0V
V 64 mA
mA VOL = 0.55V
mA VOUT = 0.0V
uA VOUT = 5.5V, All Others
GND
uA All Outputs HIGH
mA All Outputs LOW
uA All Outputs 3-STATE
3 www.fairchildsemi.com


3Pages


V320 電子部品, 半導体
AC Electrical Characteristics
(40°C to 85°C, VCC = 4.5V to 5.5V) 8 Output Switching
Symbol
From
(Input)
Mode
To
(Output)
Min
Typ
Max
Units
Output Load: CL = 50 pF, RL = 500, 8 Outputs Switching
tPLH, tPHL CLKAB/CLKBA
Register
Bus A or B
1.5
6.6 ns
tPLH, tPHL Bus A or B
Transparent
Bus A or B
1.5
6.3 ns
tPLH, tPHL SELAB/SELBA
Select Bus
Bus A or B
1.5
6.6 ns
tPLZ, tPHZ OE
Output Disable
Bus A or B
1.5
6.6 ns
tPZH, tPZL OE
Output Enable
Bus A or B
1.5
6.6 ns
tPLZ, tPHZ Direction (D)
Dir. Disable
Bus A or B
1.5
6.6 ns
tPZH, tPZL Direction (D)
Dir. Enable
Bus A or B
1.5
7.6 ns
tOSHL
Output to Output Skew (Note 6)
1.3 ns
tOSHL
Output to Output Skew (Note 6)
1.1 ns
tRISE
Transition Time, Outputs (1V to 2V)
0.5 1.5 ns
tFALL
Transition Time, Outputs (1V to 2V)
0.4 1.9 ns
Output Load: CL = 250 pF, RL = 500, 8 Outputs Switching
tPLH, tPHL CLKAB/CLKBA
Register
Bus A or B
2.5
11.2 ns
tPLH, tPHL Bus A or B
Transparent
Bus A or B
2.5
9.5 ns
tPLH, tPHL SELAB/SELBA
Select Bus
Bus A or B
2.5
11.2 ns
tPLZ, tPHZ OE
Output Disable
Bus A or B
(Note 8)
(Note 8)
ns
tPZH, tPZL OE
Output Enable
Bus A or B
2.5
11.5 ns
tPLZ, tPHZ Direction (D)
Dir. Disable
Bus A or B
(Note 8)
(Note 8)
ns
tPZH, tPZL Direction (D)
Dir. Enable
Bus A or B
2.5
13.5
ns
tOSHL
Output to Output Skew (Note 8)
2.5 ns
tOSLH
Output to Output Skew (Note 8)
2.0 ns
tRISE
Transition Time, Outputs (1V to 2V)
2.0 5.5 ns
tFALL
Transition Time, Outputs (1V to 2V)
1.4 4.4 ns
Output Load: CL = 500 pF, RL = 500, 8 Outputs Switching
tPLH, tPHL CLKAB/CLKBA
Register
Bus A or B
3.5
17.0
ns
tPLH, tPHL Bus A or B
Transparent
Bus A or B
3.5
15.9
ns
tPLH, tPHL SELAB/SELBA
Select Bus
Bus A or B
3.5
17.0
ns
tPLZ, tPHZ OE
Output Disable
Bus A or B
(Note 8)
(Note 8)
ns
tPZH, tPZL OE
Output Enable
Bus A or B
3.5
18.5
ns
tPLZ, tPHZ Direction (D)
Dir. Disable
Bus A or B
(Note 8)
(Note 8)
ns
tPZH, tPZL Direction (D)
Dir. Enable
Bus A or B
3.5
22.3
ns
tOSHL
Output to Output Skew (Note 6)
3.9 ns
tOSLH
Output to Output Skew (Note 6)
3.1 ns
tRISE
Transition Time, Outputs (1V to 2V)
4.4 7.8 ns
tFALL
Transition Time, Outputs (1V to 2V)
2.5 6.6 ns
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-
cation applies to outputs switching in the same direction also.
Note 7: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two
devices.
Note 8: 3-STATE delays are dominated by the RC Network (500 / 250 pF, or 500 / 500 pF) on the output and thus have been excluded from this
datasheet.
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共有リンク

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