|
|
PDF VSP2260 Data sheet ( Hoja de datos )
| Número de pieza | VSP2260 | |
| Descripción | CCD SIGNAL PROCESSOR for DIGITAL CAMERAS | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de VSP2260 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
|
No Preview Available !
VSP2260
VSP2260
www.ti.com
CCD SIGNAL PROCESSOR for
DIGITAL CAMERAS
FEATURES
q CCD SIGNAL PROCESSING:
Correlated Double Sampling (CDS)
Programmable Black Level Clamping
q PROGRAMMABLE GAIN AMPLIFIER (PGA):
–6dB to +42dB Gain Ranging
q 10-BIT DIGITAL DATA OUTPUT:
Up to 20MHz Conversion Rate
No Missing Codes
q 79dB SIGNAL-TO-NOISE RATIO
q PORTABLE OPERATION:
Low Voltage: 2.7V to 3.6V
Low Power: 83mW (typ) at 3.0V
Stand-By Mode: 6mW
DESCRIPTION
The VSP2260 is a complete mixed-signal processing
IC for digital cameras, providing signal conditioning
and Analog-to-Digital (A/D) conversion for the output
of a CCD array. The primary CCD channel provides
Correlated Double Sampling (CDS) to extract video
information from the pixels, –6dB to +42dB gain
range with digital control for varying illumination
conditions, and black level clamping for an accurate
black level reference. Input signal clamping and offset
correction of the input CDS are also performed. The
stable gain control is linear in dB. Additionally, the
black level is quickly recovered after gain change. The
VSP2260Y is available in an LQFP-48 package and
operates from a single +3V/+3.3V supply.
CLPDM
SHP SHD
SLOAD SCLK SDATA
RESET
ADCCK DRVDD
VCC
CCDIN
CCD
Output
Signal
Input
Clamp
Correlated
Double
Sampling
(CDS)
Serial Interface
Programmable
Gain
Amplifier
(PGA)
–6dB
to
+42dB
Timing
Control
Analog-
to-
Digital
Converter
Output
Latch
10-Bit
Digital
Output
B[9:0]
Preblanking
Optical Black (OB)
Level Clamping
Reference Voltage Generator
PBLK
COB
CLPOB
BYPP2 BYP BYPM REFN
CM
REFP DRVGND GNDA
Copyright © 2000, Texas Instruments Incorporated
SBMS010
Printed in U.S.A. November, 2000
1 page  
CDS TIMING SPECIFICATIONS
CCD
Output
Signal
SHP(1)
SHD(1)
ADCCK
N
tWP
tPD
tWD
tDP
tINHIBIT
N+1
tS
tADC
tS
tADC
tHOLD
tOD
B[9:0]
N – 11
N – 10
N–9
N+2
tCKP
tCKP
tCKP
N–8
N+3
N–7
SYMBOL
tCKP
tADC
tWP
tWD
tPD
tDP
tS
tINHIBIT
tHOLD
tOD
DL
PARAMETER
Clock Period
ADCCK HIGH/LOW Pulse Width
SHP Pulse Width
SHD Pulse Width
SHP Trailing Edge to SHD Leading Edge(1)
SHD Trailing Edge to SHP Leading Edge(1)
Sampling Delay
Inhibited Clock Period
Output Hold Time
Output Delay
Data Latency, Normal Operation Mode
MIN TYP MAX UNITS
48 ns
20 ns
14 ns
11 ns
8 ns
12 ns
5 ns
20 ns
7 ns
38 ns
9 (fixed)
Clock Cycles
NOTE: (1) The description and timing diagrams in this data sheet are all based on the polarity of Active LOW
(default value). The user can select the active polarity (Active LOW or Active HIGH) through the serial interface.
Refer to the “Serial Interface” section for more detail.
VSP2260
SBMS010
5
5 Page 
TIMINGS
The CDS and the ADC are operated by SHP/SHD and their
derivative timing clocks generated by the on-chip timing
generator. The digital output data is synchronized with
ADCCK. See the VSP2260 “CDS Timing Specifications” for
the timing relationship among the CCD signal, SHP/SHD,
ADCCK and the output data. CLPOB is used to activate the
black level clamp loop during the OB pixel interval, and
CLPDM is used to activate the input clamping during the
dummy pixel interval. If the CLPDM pulse is not available in
your system, the CLPOB pulse can be used in place of
CLPDM as long as the clamping takes place during black
pixels (refer to the “Input Clamp and Dummy Pixel Clamp”
section for more detail). The clock polarities of SHP/SHD,
CLPOB and CLPDM can be independently set through the
serial interface (refer to the “Serial Interface” section for more
detail). The descriptions and the timing diagrams in this data
sheet are all based on the polarity of Active LOW (default
value). In order to keep a stable and accurate OB clamp level,
we recommend CLPOB should not be activated during PBLK
active period. Refer to the “Preblanking and Data Latency”
section for more detail. In Stand-By mode, ADCCK, SHP,
SHD, CLPOB and CLPDM are internally masked and pulled
HIGH.
POWER-SUPPLY, GROUNDING, AND DEVICE
DECOUPLING RECOMMENDATIONS
The VSP2260 incorporates analog circuitry and a very
high-precision, high-speed ADC that are vulnerable to any
extraneous noise from the rails or elsewhere. For this reason,
it should be treated as an analog component and all supply
pins except for DRVDD should be powered by the only
analog supply of the system. This will ensure the most
consistent results, since digital power lines often carry high
levels of wideband noise that would otherwise be coupled
into the device and degrade the achievable performance.
Proper grounding, short lead length, and the use of ground
planes are also very important for high-frequency designs.
Multi-layer PC boards are recommended for the best perfor-
mance, since they offer distinct advantages like minimizing
ground impedance, separation of signal layers by ground
layers, etc. It is highly recommended that analog and digital
ground pins of the VSP2260 be joined together at the IC and
be connected only to the analog ground of the system. The
driver stage of the digital outputs (B[9:0]) is supplied through
a dedicated supply pin (DRVDD) and it should be separated
from the other supply pins completely, or at least with a
ferrite bead.
It is also recommended to keep the capacitive loading on the
output data lines as low as possible (typically less than
15pF). Larger capacitive loads demand higher charging
current surges that can feed back into the analog portion of
the VSP2260 and affect the performance. If possible, exter-
nal buffers or latches should be used, providing the added
benefit of isolating the VSP2260 from any digital noise
activities on the data lines. In addition, resistors in series
with each data line may help minimize the surge current.
Values in the range of 100Ω to 200Ω will limit the instan-
taneous current the output stage has to provide for recharg-
ing the parasitic capacitances as the output levels change
from LOW to HIGH, or HIGH to LOW. Due to high
operation speed, the converter also generates high-frequency
current transients and noises that are fed back into the supply
and reference lines. This requires the supply and reference
pins to be sufficiently bypassed. In most cases, 0.1µF ce-
ramic chip capacitors are adequate to decouple the reference
pins. Supply pins should be decoupled to the ground plane
with a parallel combination of tantalum (1µF to 22µF) and
ceramic (0.1µF) capacitors. The effectiveness of the decou-
pling largely depends on the proximity to the individual pin.
DRVDD should be decoupled to the proximity of DRVGND.
Special attention must be paid to the bypassing of COB,
BYPP2 and BYPM, since these capacitor values determine
important analog performances of the device.
VSP2260
SBMS010
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet VSP2260.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| VSP2260 | CCD SIGNAL PROCESSOR for DIGITAL CAMERAS | Burr-Brown Corporation |
| VSP2260Y | CCD SIGNAL PROCESSOR for DIGITAL CAMERAS | Burr-Brown Corporation |
| VSP2262 | VSP2262 CCD Signal Processor for Digital Cameras (Rev. A) |  Texas Instruments |
| VSP2262K | CCD SIGNAL PROCESSOR for DIGITAL CAMERAS | Burr-Brown Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |