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VSP2080 の電気的特性と機能

VSP2080のメーカーはBurr-Brown Corporationです、この部品の機能は「CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS」です。


製品の詳細 ( Datasheet PDF )

部品番号 VSP2080
部品説明 CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS
メーカ Burr-Brown Corporation
ロゴ Burr-Brown Corporation ロゴ 




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VSP2080 Datasheet, VSP2080 PDF,ピン配置, 機能
®
VSP2080 ®
VSP2080
TM CCD SIGNAL FRONT-END
PROCESSOR FOR DIGITAL CAMERAS
FEATURES
q CCD SIGNAL PROCESSING
Correlated Double Sampling
Black Level Clamping
0 to +34dB Gain Range
55dB SNR Referred to Full Scale
q SELECTABLE LOGIC-INPUT POLARITY
Positive Active or Negative Active
q PORTABLE OPERATION
Low Voltage: 2.7V to 3.6V
Low Power: 144mW at 3.0V
Power-Down Mode: 10mW
APPLICATIONS
q VIDEO CAMERAS
q DIGITAL STILL CAMERAS
q PC CAMERAS
q SECURITY CAMERAS
REFCK DATCK
DESCRIPTION
The VSP2080 is a complete front-end processing IC
for digital cameras. The VSP2080 provides signal
conditioning for the output of a CCD array. The
VSP2080 provides correlated double sampling to ex-
tract the video information from the pixels, 0dB to
+34dB gain range with analog control for varying
illumination conditions, and black level clamping for
an accurate black reference. The stable gain control is
linear in dB. Additionally, the black level quickly
recovers after screen changes. The MODE pin allows
the selection of logic-input polarity. The VSP2080 is
available in a 20-lead TSSOP package.
MODE
AGC IN
C
OB
CCD
OUT
CCD D
Clamp
Correlated
Double
Sampling
Logic Input
Polarity
Control
+6dB
Log
VCA
Optical
Black Level
Auto-Zero
+28dB
OUT
CCD R
Dummy
Pixel
Auto-Zero
Internal
Bias
Generator
DUMC
REFT REFB REF IN
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-1498B
Printed in U.S.A. August, 1999

1 Page





VSP2080 pdf, ピン配列
PIN CONFIGURATION
Top View
TSSOP
LCM 1
2.4V 2
OUT 3
C4
MODE 5
OB 6
REFCK 7
DATCK 8
DUMC 9
PD 10
VSP2080T
20 REF IN
19 REFB
18 REFT
17 VDDA
16 AGC IN
15 GNDA
14 CCD R
13 CCD D
12 GNDA
11 VDDA
ABSOLUTE MAXIMUM RATINGS
+VS ....................................................................................................... +6V
Analog Input .......................................................... –0.3V to (+VDDA +0.3V)
Logic Input ............................................................ –0.3V to (+VDDA +0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
PIN DESCRIPTIONS
PIN DESIGNATOR
TYPE
DESCRIPTION
1 LCM
Bypass
Attenuator Common-Mode Bypass,
Bypass to GND with 0.1µF capacitor
2 2.4V
Bypass
Attenuator Ladder Bypass,
Bypass to GND with 0.1µF capacitor
3
OUT
Analog Output Analog Output
4C
Capacitor
Capacitor for Optical Black Auto-Zero
Loop
5 MODE Logic Input Mode Control for Logic Input:
LO = Positive Pulse Active
HI = Negative Pulse Active
6 OB Logic Input Optical Black Clamp Pulse
7 REFCK Logic Input Sampling Pulse for Reset
8 DATCK Logic Input Sampling Pulse for Data
9 DUMC Logic Input Dummy Pixel Clamp Pulse
10 PD
Logic Input
Power-Down Control:
LO = Normal Operation
HI = Reduced Power
11 VDDA Power Supply Positive Power Supply
12 GNDA
Ground
Analog Ground
13 CCD D
Analog Input CCD Signal Input
14 CCD R
Capacitor Capacitor for Dummy Feedback Loop
15 GNDA
16 AGC IN
Ground
Analog Input
Analog Ground
Sets Gain of Gain Control Amp.
17 VDDA Power Supply Positive Power Supply
18 REFT
Bypass
Bypass for Internal Top Reference
19 REFB
Bypass
Bypass for Internal Bottom Reference
20 REF IN
Analog Input External Reference Input (1.0V)
PACKAGE/ORDERING INFORMATION
PRODUCT
VSP2080T
"
PACKAGE
20-Lead TSSOP
"
PACKAGE
DRAWING
NUMBER(1)
353
"
SPECIFIED
TEMPERATURE
RANGE
–25°C to +85°C
"
PACKAGE
MARKING
VSP2080T
"
ORDERING
NUMBER(2)
VSP2080T
VSP2080T/2K
TRANSPORT
MEDIA
250-Piece Tray
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP2080T/2K” will get a single 2000-
piece Tape and Reel.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
3 VSP2080


3Pages


VSP2080 電子部品, 半導体
DIFFERENCE AMPLIFIER
The correlated double sampler function is completed when
the output of the data and reference channel are sent to the
difference amplifier where the signals are subtracted. In
addition to providing the difference function, the difference
amplifier amplifies the signal by a factor of 2 which helps
to improve the overall signal-to-noise ratio. The difference
amplifier also generates a differential signal to drive the
voltage-controlled attenuator.
be considered as the loop operates in a sampled mode. Opera-
tion of the dummy auto-zero loop is activated by the DUMC
signal that happens once during each horizontal line interval.
TIMING
The REFCK and DATCK signals are used to operate the
CDS as previously explained. The input digital timing sig-
nals REFCK, DATCK, DUMC and OB are capable of being
driven from either 3V or 5V logic levels.
INPUT CLAMP
The output from the CCD array is capacitively coupled to the
VSP2080. To prevent shifts in the DC level from taking place
due to varying input duty cycles, the input capacitor is
clamped during the dummy pixel interval by the REFCK
signal. A P-channel transistor is used for this input clamp
switch to be able to allow a 2V negative change at the input
that would bring the signal below ground by 1V. Under
typical conditions, the black level at the input to the VSP2080
is at 1V.
DUMMY PIXEL AUTO-ZERO LOOP
The output from the data and reference channel is processed
by the previously mentioned difference amplifier. The dif-
ferential output from the difference amplifier is sent to both
the voltage-controlled logarithmic attenuator and to an error
amplifier. The error amplifier amplifies and feeds a signal to
the difference amplifier to drive the offset measured at the
output of the difference amplifier to zero. A block diagram
of this circuit is shown in Figure 3. This error amplifier
serves the purpose of reducing the offset of the CDS to avoid
a large offset from being amplified by the output amplifier.
The effective time constant of this loop is given by:
T = R•C
A•D
where R is 10k, C is an external capacitor connected to
CCD R (pin 14), A is the gain of the error amplifier with a
value of 50, and D is the duty cycle of the time that the dummy
pixel auto-zero loop is in operation. The duty cycle (D) must
CCD D
CDS
To VCA
VOLTAGE-CONTROLLED ATTENUATOR
To maximize the dynamic range of the VSP2080, a voltage-
controlled attenuator is included with a control range from
0dB to –34dB. The gain control has a logarithmic relation-
ship between the control voltage and the attenuation. The
attenuator processes a differential signal from the difference
amplifier to improve linearity and to reject both power supply
and common-mode noise. The output from the attenuator is
amplified by 28dB prior to being applied to the A/D. A typical
gain control characteristic of the VSP2080 is shown in the
typical performance curve, “Gain Control Characteristics”.
BLACK LEVEL AUTO-ZERO LOOP
The black level auto-zero loop amplifies the difference
between the output of the output amplifier and a reference
signal during the dummy pixel interval. This difference
signal is amplified and fed back into the output amplifier to
correct the offset. In doing so, the output level of the entire
CCD channel can be controlled to be approximately –FS +
31mV under zero signal conditions. The black level auto-
zero loop is activated by the OB timing signal. Figure 4
shows a block diagram of the black level auto-zero loop. The
loop time constant is given by:
T= C
GM D
where C is the external filter capacitance applied to C (pin 4),
GM is .001 Siemens (inverse ohm) and D is the duty cycle
of the time that the black level auto-zero loop is in operation.
The duty cycle (D) must be considered as the loop operates
in a sampled mode. Operation of the black level auto-zero
loop is activated by the OB signal that happens once during
each horizontal line interval.
Output Amplifier
CCD R
CEXT
A Error
Amplifier
R
DUMC
From
VCA
CEXT
C
OUT
1.03 • REF IN
GM Error
Amplifier
OB
FIGURE 3. Simplified Block Diagram of Dummy Pixel
Loop.
®
FIGURE 4. Simplified Block Diagram of Optical Black
Level Auto-Zero Loop.
VSP2080
6

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共有リンク

Link :


部品番号部品説明メーカ
VSP2080

CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS

Burr-Brown Corporation
Burr-Brown Corporation
VSP2080T

CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS

Burr-Brown Corporation
Burr-Brown Corporation


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