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Número de pieza | VSP2000 | |
Descripción | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS | |
Fabricantes | Burr-Brown Corporation | |
Logotipo | ||
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VSP2000
VSP2000
TM CCD SIGNAL PROCESSOR
FOR DIGITAL CAMERAS
FEATURES
q CCD SIGNAL PROCESSING
Correlated Double Sampling
Black Level Clamping
0 to +34dB Gain Ranging
High SNR: 53dB
q 10-BIT A/D CONVERSION
Up to 18MHz Conversion Rate
No Missing Codes
q PORTABLE OPERATION
Low Voltage: Down to 2.7V
Low Power: 150mW at 2.7V
APPLICATIONS
q VIDEO CAMERAS
q DIGITAL STILL CAMERAS
q PC CAMERAS
q SECURITY CAMERAS
REFCK DATCK
DESCRIPTION
The VSP2000 is a complete digital camera IC, provid-
ing signal conditioning and 10-bit analog-to-digital
conversion for the output of a CCD array. The primary
CCD channel provides correlated double sampling to
extract the video information from the pixels, 0dB to
+34dB gain range with analog control for varying
illumination conditions, and black level clamping for
an accurate black reference. The stable gain control is
linear in dB. Additionally, the black level is quickly
recovered after gain changes. The VSP2000 is avail-
able in a 48-lead LQFP package and operates from a
single +3V supply.
AGC1 AGC2
C
OB
ADCK
CCD D
CCD R
Clamp
T/H
T/H
+6dB
T/H
Dummy
Pixel
Auto-Zero
Black
Level
Auto-Zero
VCA
+28dB
A/D
Timing
Control
10-Bit
18MHz
A/D
Output
Latch
10-Bit
Digital
Output
REF
DUMC
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-11432A
VPSriPnte2d i0n U0.S0.A. April, 1998
®
1 page TIMING DIAGRAMS (CONT)
18MHz
0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns
RESET
HI
27.7 55.5
CCD OUT
REFCK
DATCK
18 32
46
60
ADCK
OB
DUMC
18
24
64
OUTPUT DATA
DATA VALID
50 58
DATA VALID
DATA VALID
ADCK OUTPUT TIMING
REFCK
DATCK
A/D CLOCK
(Internal)
A/D DATA OUT
(Internal)
ADCK
OUTPUT DATA
t0
t1 t2
t3
t4
t5
t6
t7
SYMBOL
PARAMETER
MIN TYP MAX UNITS
t0
ADCK Clock Period
55.6
ns
t1 REFCK Pulse Width
14 ns
t2 DATCK Pulse Width
14 ns
t3
DATCK Delay
27 28 29 ns
t4
A/D Clock Delay (Internal)
26 28 30 ns
t5
A/D Data Out Delay (Internal) 1.5 2.0 2.5
ns
t6
ADCK Delay
–25 0 25 ns
t7
Output Data Delay
7.1 8.3 9.5
ns
NOTE: Timing Specifications = TMIN to TMAX with DRVDD = 3.0V, ADVDD = 3.0V, DVDD = 3.0V.
18MHz timing shown for reference.
5 VSP2000
®
5 Page FIGURE 7a. Evaluation Board Silkscreen (top).
FIGURE 7b. Evaluation Board Layout.
11
VSP2000
®
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet VSP2000.PDF ] |
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