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VSC7125QN の電気的特性と機能

VSC7125QNのメーカーはETCです、この部品の機能は「1.0625 Gbits/sec Fibre Channel Transceiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 VSC7125QN
部品説明 1.0625 Gbits/sec Fibre Channel Transceiver
メーカ ETC
ロゴ ETC ロゴ 




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VSC7125QN Datasheet, VSC7125QN PDF,ピン配置, 機能
Data Sheet
VSC7125
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre
Channel Transceiver
Features
• ANSI X3T11 Fibre Channel Compatible
1.0625 Gbps Full-duplex Transceiver
• 10 Bit TTL Interface for Transmit and
Receive Data
• Monolithic Clock Synthesis and Clock
Recovery - No External Components
• 106.25 MHz TTL Reference Clock
• Low Power Operation - 650 mW
• Suitable for Both Coaxial and Optical
Link Applications
• 64 Pin, 10mm or 14mm PQFP
• Single +3.3V Power Supply
General Description
The VSC7125 is a full-speed Fibre Channel Transceiver optimized for Disk Drive and other space con-
strained applications. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency.
The VSC7125 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data,
deserializes it onto the 10-bit receive data bus, outputs two recovered clocks at one twentieth of the incoming
baud rate and detects Fibre Channel “Comma” characters. The VSC7125 contains on-chip PLL circuitry for
synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These cir-
cuits are fully monolithic and require no external components.
VSC7125 Block Diagram
EWRAP
R0:9
RCLK
RCLKN
COM_DET
EN_CDET
T0:9
10
QD
Serial to
Parallel
÷ 10
÷ 20
Resync Frame
Logic
Comma
Detect
Retimed
Data
QD
Recovered
Clock
Clock
Recovery
2:1
10
DQ
Parallel
to Serial
Serial Data
Synthesized
Clock
DQ
RX+
RX-
TX+
TX-
REFCLK
PLL Clock
Multiply
G52121-0, Rev. 4.1
4/23/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1

1 Page





VSC7125QN pdf, ピン配列
Data Sheet
VSC7125
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre
Channel Transceiver
resulting parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and
RCLKN. In order to maximize the setup and hold times available at this interface, the parallel data is loaded
into the output register at a point nominally midway between the transition edges of RCLK and RCLKN.
If serial input data is not present, or does not meet the required baud rate, the VSC7125 will continue to
produce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output
frequency under these circumstances may differ from their expected frequency by no more than +1%.
Word Alignment
The VSC7125 provides 7-bit Fibre Channel comma character recognition and data word alignment. Word
synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7125 con-
stantly examines the serial data for the presence of the Fibre Channel “comma” character. This pattern is
“0011111XXX”, where the leading zero corresponds to the first bit received. The comma sequence is not con-
tained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special
characters, known as K28.1, K28.5 and K28.7, which is defined specifically for synchronization in Fibre Chan-
nel systems. Improper alignment of the comma character is defined as any of the following conditions:
1) The comma is not aligned within the 10-bit transmission character such that T0...T6 = “0011111”
2) The comma straddles the boundary between two 10-bit transmission characters.
3) The comma is properly aligned but occurs in the received character presented during the rising edge of
RCLK rather than RCLKN.
When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in
such a manner that the comma character is aligned properly in R0:9. This results in proper character and half-
word alignment. When the parallel data alignment changes in response to an improperly aligned comma pattern,
some data which would have been presented on the parallel output port may be lost. However, the synchroniza-
tion character and subsequent data will be output correctly and properly aligned. When EN_CDET is LOW, the
current alignment of the serial data is maintained indefinitely, regardless of data pattern.
On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the
parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma char-
acter and has a duration equal to the data, or half of an RCLK period. The COM_DET signal is timed such that
it can be captured by the adjoining protocol logic on the rising edge of RCLKN. Functional waveforms for syn-
chronization are given in Figure 2 and Figure 3. Figure 2 shows the case when a comma character is detected
and no phase adjustment is necessary. It illustrates the position of the COM_DET pulse in relation to the comma
character on R0:9. Figure 3 shows the case where the K28.5 is detected, but it is out of phase and a change in
the output data alignment is required. Note that up to three characters prior to the comma character may be cor-
rupted by the realignment process.
G52121-0, Rev. 4.1
4/23/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3


3Pages


VSC7125QN 電子部品, 半導体
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre
Channel Transceiver
Data Sheet
VSC7125
Table 2: Receive AC Characteristics
Parameters
T1
T2
T3
T4
Description
Data or COM_DET Valid
prior to RCLK/RCLKN
rise
Data or COM_DET Valid
after RCLK or RCLKN
rise
Deviation of RCLK
rising edge to RCLKN
rising edge delay from
nominal.
delay=
-f---b---a--u---d-
10
±
T3
Deviation of RCLK,
RCLKN frequency from
nominal.
f RCLK=
-f---R---E----F---C---L---K--
2
±
T
4
Min.
4.0
3.0
-500
-1.0
Max.
Units
Conditions
ns. Measured between the
1.4V point of RCLK or
RCLKN and a valid level
of R0:9. All outputs
ns. driving 10pF load.
Nominal delay is 10 bit
500 ps. times. Tested on sample
basis
Whether or not locked to
1.0 % serial data
TR, TF
R0:9, COM_DET, RCLK,
RCLKN rise and fall time
Rlat
TLOCK
Latency from RX to R0:9
Data acquisition lock time
@ 1.0625Gb/s
Receive Data Jitter Power
Receive Data
Jitter
-2----×-----B----i-1-t--T----i--m-----e-
PhaseNoise
100 K H z
15bc + 2ns
2.4
34bc + 2ns
2.4
40
ns.
Between Vil(max) and
Vih(min), into 10 pf. load.
bc = Bit clock
ns = Nano second
µs.
8B/10B IDLE pattern.
Tested on a sample basis
dBc, RMS for l0-12 Bit
ps. Error Ratio Tested on a
sample basis
Note: Probability of recovery for data acquisition is 95% per section 5.3 of the FC-PH rev. 4.3.
Page 6
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52121-0, Rev. 4.1
4/23/98

6 Page



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部品番号部品説明メーカ
VSC7125QN

1.0625 Gbits/sec Fibre Channel Transceiver

ETC
ETC
VSC7125QU

1.0625 Gbits/sec Fibre Channel Transceiver

ETC
ETC


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