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VSC7123QU の電気的特性と機能

VSC7123QUのメーカーはETCです、この部品の機能は「10-Bit Transceiver for Fibre Channel and Gigabit Ethernet」です。


製品の詳細 ( Datasheet PDF )

部品番号 VSC7123QU
部品説明 10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
メーカ ETC
ロゴ ETC ロゴ 




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VSC7123QU Datasheet, VSC7123QU PDF,ピン配置, 機能
VELOCITYTM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
Features
• 802.3z Gigabit Ethernet-Compliant
1.25 Gb/s Transceiver
• ANSI X3T11 Fibre Channel-Compliant
1.0625 Gb/s Transceiver
• 0.98 to 1.36 Gb/s Full-Duplex Operation
• 10-Bit TTL Interface for Transmit and
Receive Data
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
• Automatic Lock-to-Reference
• RX Cable Equalization
• Analog/Digital Signal Detection
• JTAG Access Port for Testability
• Single +3.3V Supply, 650mW Typical
• Packages: 64-Pin 10mm and 14mm PQFP and
10mm TQFP
General Description
The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard
pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK
frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit
(CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty
clocks. The VSC7123 receiver detects “Comma” characters for frame alignment. An analog/digital signal
detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for
InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher
performance, lower cost replacement for the VSC7125 and VSC7135.
VSC7123 Block Diagram
R(0:9)
10
RCLK
RCLKN
COMDET
ENCDET
EWRAP
SIGDET
T(0:9)
10
REFCLK
QD
Serial to
Q Parallel D
QD
Comma
Detect
÷10 Clock
÷20 Recovery
2:1
Signal
Detect
RX+
RX-
DQ
x10 Clock
Multiply
Parallel
to Serial
DQ
TX+
TX-
NOT SHOWN: JTAG Boundary Scan
G52212-0, Rev 4.3
03/25//01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected]
Internet: www.vitesse.com
Page 1

1 Page





VSC7123QU pdf, ピン配列
VELOCITYTM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
serial data is retimed, deserialized and output on R(0:9). The parallel data will be captured by the adjoining
protocol logic on the rising edges of RCLK and RCLKN.
If serial input data is not present or does not meet the required baud rate, the VSC7123 will continue to
produce a recovered clock, allowing downstream logic functionality to continue. Under these circumstances,
the RCLK/RCLKN output frequency differ from its expected frequency by no more than +1%.
Word Alignment
The VSC7123 provides 7-bit comma character recognition and data word alignment. Word synchronization
is enabled by asserting ENCDET HIGH. When synchronization is enabled, the receiver examines the recovered
serial data for the presence of the “Commacharacter. This pattern is 0011111XXX, where the leading zero
corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data
character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and
K28.7, which are defined for synchronization purposes. Improper alignment of the comma character is defined
as any of the following conditions:
1) The comma is not aligned within the 10-bit transmission character such that R0...R6 = 0011111.
2) The comma straddles the boundary between two 10-bit transmission characters.
3) The comma is properly aligned but occurs in the received character presented during the rising edge of
RCLK rather than RCLKN.
When ENCDET is HIGH and an improperly aligned comma is encountered, the recovered clock is
stretched (never slivered) so that the comma character and recovered clocks are properly aligned to R(0:9). This
results in proper character and word alignment. When the parallel data alignment changes in response to a
improperly aligned comma pattern, some data which would have been presented on the parallel output port may
be lost. Additionally, the first Comma pattern may also be lost or corrupted. Subsequent data will be output
correctly and properly aligned. When ENCDET is LOW, the current alignment of the serial data is maintained
indefinitely, regardless of data pattern.
When encountering a comma character, COMDET is driven HIGH. The COMDET pulse is presented
simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The
COMDET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of
RCLKN. Functional waveforms for synchronization are given in Figure 2 and Figure 3. Figure 2 shows the case
when a comma character is detected and no phase adjustment is necessary. Figure 2 illustrates the position of
the COMDET pulse in relation to the comma character on R(0:9). Figure 3 shows the case where the K28.5 is
detected, but it is misaligned so a change in the output data alignment is required. Note that up to three
characters prior to the comma character may be corrupted by the realignment process.
G52212-0, Rev 4.3
03/25//01
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: [email protected]
Internet: www.vitesse.com
Page 3


3Pages


VSC7123QU 電子部品, 半導体
VELOCITYTM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Figure 4: Transmit Timing Waveforms
REFCLK
T1 T2
T(0:9)
Data Valid
Data Valid
Data Valid
Data Sheet
VSC7123
Table 2: Transmit AC Characteristics
Parameters
T1
T2
TSDR,TSDF
TLAT
RJ
DJ
Description
Min Typ Max Units
T(0:9) Setup time to the rising
edge of REFCLK
1.5 — — ns
T(0:9) hold time after the rising
edge of REFCLK
1.0
ns
TX+/TX- rise and fall time
— — 300 ps
Latency from rising edge of
REFCLK to T0 appearing on
TX+/TX-
8bc
8bc+
4ns
ns
Transmitter Output Jitter Allocation
Random jitter (RMS)
5 8 ps.
Serial data output deterministic
jitter (pk-pk)
30 80 ps.
Conditions
Measured between the valid data
level of T(0:9) to the 1.4V point
of REFCLK.
20% to 80%, 50load to
VDD-2.0.
bc = Bit clocks
ns = Nano second
Measured at SO+/-, 1 sigma
deviation of 50% crossing point.
IEEE 802.3Z Clause 38.68,
tested on a sample basis.
Page 6
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: [email protected]
Internet: www.vitesse.com
G52212-0, Rev 4.3
03/25/01

6 Page



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部品番号部品説明メーカ
VSC7123QN

10-Bit Transceiver for Fibre Channel and Gigabit Ethernet

ETC
ETC
VSC7123QU

10-Bit Transceiver for Fibre Channel and Gigabit Ethernet

ETC
ETC


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