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VP553 の電気的特性と機能

VP553のメーカーはSanyo Semicon Deviceです、この部品の機能は「CRT Display Video Output Amplifier」です。


製品の詳細 ( Datasheet PDF )

部品番号 VP553
部品説明 CRT Display Video Output Amplifier
メーカ Sanyo Semicon Device
ロゴ Sanyo Semicon Device ロゴ 




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VP553 Datasheet, VP553 PDF,ピン配置, 機能
www.DataSheet4U.com
Ordering number : EN5350A
Wideband Output Module (Video Pack)
VP553
CRT Display Video Output Amplifier
Features
• Active load circuits
• Wide bandwidth and high output voltage. Optimal for
use in fH (horizontal deflection frequency) = 90 kHz
class ultrahigh precision monitors.
• Single 15-pin SIP molded package houses three
channels.
Package Dimensions
unit: mm
2127A
[VP553]
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Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Allowable power dissipation
Maximum junction temperature
Maximum case temperature
Storage temperature
Symbol
VCC max
Pd max
Tj max
Tc max
Tstg
Conditions
With an ideal heat sink at Ta = 25°C
DataShee
Ratings
90
25
150
100
–20 to +110
Unit
V
W
°C
°C
°C
Operating Conditions at Ta = 25°C
Parameter
Recommended supply voltage
Symbol
VCC
Conditions
Ratings
80
Unit
V
Electrical Characteristics at Ta = 25°C (For a single channel, with Rin = 680 , Rip = 22 , Cip = 56 pF)
Parameter
Clock frequency bandwidth (–3 dB)
Frequency bandwidth (–3 dB)
Pulse response
Voltage gain
Current drain
Symbol
Conditions
f (clock)
fc
tr
tf
VG (DC)
VCC = 80 V, CL = 10 pF
VIN (DC) = 2.0 V, VOUT (p-p) = 40 V
VCC = 80 V, CL = 10 pF
VIN (DC) = 2.0 V, VOUT (p-p) = 40 V
ICC(1)
ICC(2)
VCC = 80 V, VIN (DC) = 2.0 V, f = 10 MHz
clock, CL = 10 pF, VOUT (p-p) = 40 V
VCC = 80 V, VIN (DC) = 2.0 V, f = 100 MHz
clock, CL = 10 pF, VOUT (p-p) = 40 V
min
13
Ratings
typ
160
80
4.8
4.5
15
32
75
max
17
Unit
MHz
MHz
ns
ns
Double
mA
mA
DataSheet4U.com SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
13097HA (OT) No. 5350-1/5
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VP553 pdf, ピン配列
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VP553
et4U.com
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DataShee
Thermal Design
Thermal design requires that the two conditions Tj (max) 150°C and Tc 100°C be met.
(a) Concerning Tj (max), the chip temperature Tj for each transistor is given by equation (1).
Tj = (Tri) = θj–c (Tri) × PC (Tri) + Tc + Ta (°C) ................................................(1)
θj–c (Tri): The thermal resistance of each transistor chip itself
PC (Tri): The collector loss for each transistor
Tc: Increase in the case temperature
Ta: Ambient temperature
θj–c (Tri) for each chip will be:
θj–c (Tr1) to (Tr4) = 35°C/W ................................................................................(2)
The loss in transistors in a video pack varies with frequency. The loss increases with the frequency.
For example, if the maximum frequency will be 100 MHz (clock), then the transistors with the largest losses will be
transistors 3 and 4 in the emitter-follower (EF) stage. From the Pd – f (clock) figure, we see that that loss will be 25%
of the total for a single channel. That is:
PC (EF stage) f = 100 MHz = Pd (1ch) f = 100 MHz × 0.25 [W]..................................(3)
The thermal design must assure that Tj does not exceed 150°C at this time.
(b) Concerning Tc (max), the relationship between θh and Tc is:
Tc = Pd (total) × θh .............................................................................................(4)
Taking the increase due to Ta into account, the condition the thermal design must meet becomes Tc = Tc + Ta <
100°C.
DataSheet4U.coNmext we design thermal conditions for the VP553 that meet the conditions in sections (a) and (b) above.
DataSheet4 U .com
No. 5350-3/5


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