PDF VP2615 Data sheet ( Hoja de datos )

Número de pieza	VP2615
Descripción	H.261 Decoder
Fabricantes	Mitel Networks Corporation
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No Preview Available ! Supersedes January 1996 edition, DS3479 - 3.0 VP2VP6216155 H.261 Decoder DS3479 - 4.0 June 1996 FEATURES s Inputs run length coded transform data s Outputs 8 bit pixels in YUV block format s Up to full CIF resolution and 30 Hz frame rates s Supports motion compensation with up to 15 pixel movement s On chip frame store controller s 100 pin QFP package ASSOCIATED PRODUCTS s VP510 Colour Space Converter s VP520S Three Channel Video Filter s VP2611 Integrated H261 Encoder s VP2612 Video Multiplexer s VP2614 Video Demultiplexer DESCRIPTION The VP2615 decoder forms part of a chip set for use in video conferencing and video telephony applications. It conforms to the CCITT H261 standard, and will decode data coded with full or quarter CIF resolution at frame rates up to 30 Hz. It accepts run length coded coefficients which have already been error corrected and Huffman decoded, and produces multiplexed YUV data in macro block format after a pipeline delay of two MacroBlocks. As shown in Figure 1, other devices in the chip set then convert this data into full resolution, component or composite, video. The incoming run length coded data is converted to individual coefficient values in the correct order. Data reconstruction is then performed on a block by block basis by multiplying the quantized coefficients with the original quantization value, and then applying the inverse cosine transform. In the inter frame mode this data is then added to the motion compensated block from the previous frame. This block can be passed through a low pass filter when required. A frame store controller produces addresses which allow the best fit block to be read from the frame store, and which also allow the store to be updated with reconstructed data. Refresh cycles are generated when necessary. SYSTEM CONTROLLER USER INTERFACE H261 BIT STREAM VP2614 VIDEO DEMUX RECEIVE BUFFER 32K X 8 RLC DATA ADR VP2615 VIDEO DECODER CIF FRAME STORE 128K X 16 FRMOUT VP520 3 CHANNEL VIDEO FILTER Y/CR/CB MACRO BLOCK DATA ADR DATA TWO CIF FRAME STORES 256K X 16 VP530 NTSC/PAL ENCODER VP510 COLOUR SPACE CONVERTER COMP NTSC/PAL RGB OUTPUTS Fig 1 : Typical Video Conferencing Receiver 1 1 page (between 2 and 62 with DIN4 as MSB ), which has been used for this macroblock. If no new value is provided for a macroblock then the old value is re-used. Horizontal MV: This input (on DIN4:0 ) represents the horizon- tal component of the motion vector. It must always be provided when motion compensated Inter coding is in use. Vertical MV: This input (On DIN4:0) represents the vertical component of the the motion vector. It must always be provided when motion compensated Inter coding is in use. Sub Blk No: Each macroBlock contains 6 Sub-blocks, num- bered 1 through 6. The corresponding binary value should be provided on DIN2:0, before the RLC coefficients of that Sub-Block appear. If a Sub-Block contains no coefficients, then its number need not be provided at all, or it can be immediately followed by the next sub block number with- out any intermediate coefficient values. Even though zero valued sub blocks can simply be ignored in this way, a 2048 clock delay between new macroblocks must still be maintained by the video de-multiplexer. Zero Run Count: The number of zero valued coefficients preceding the (non-zero) RLC coefficient is defined by this input. DIN 6 and 7 are not used, with the value between 0 and 63 defined by DIN5:0. RLC Coefficient: This input defines the value of the run length coded coefficient. It will always be a non-zero value Wait State: This mode should be used on any cycle where no data is being input at the DIN port. Wait States can be SUBBLOCK ORDER WITHIN MACROBLOCK 12 34 Y 5 U 6 V PIXEL ORDER WITHIN SUBBLOCK 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 0139 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Fig 5 : Ordering of Pixels within MacroBlock VP2615 SYSCLK FRMOUT MBOUT VPIX YUV Pixel 0 Pixel 1 Pixel 2 Pixel 383 Fig 6 : YUV Port Timing inserted between any other instructions as required. Any undefined bits in the above descriptions may be made high or low as desired. The first information supplied for a macroblock should be that contained within the Control Decisions byte. Receipt of this instruction resets the internal cycle counter for that MacroBlock. Although some Macro Blocks may contain no data, the VP2615 requires that at least the Control Decisions, GOB Number and Macro Block Number be supplied by the de-multiplexer ( in that order ). All other side information, which is to be provided for a non zero block, must then be supplied before any sub block data can be accepted. GOB's and Macroblocks must be supplied in the correct sequence, but sub blocks within a macroblock can be in any order. The VP2615 does not need to be explicitly informed that the last coefficient has been received within a sub-block. It will wait for a new sub-block number, or a new Macroblock Control Deci- sion Byte, before processing the previous sub-block since it then knows that the sub block is complete. At least 2048 SYSCLK cycles must separate the start of one Macro Block (identified by receipt of the Control Decisions byte) from the start of the following Macro Block. There are, however, no specific restrictions on the timing of Sub-Blocks within the MacroBlock. The minimum gap between incoming macroblocks is needed for internal processing and also for the time to output 384 decoded values at one quarter the SYSCLK frequency. The VP2615 contains two complete macro block buffers in its input circuitry, which swap on the completion of the process- ing and outputting of the results. Whilst one is used internally the other can be loaded with a new macroblock. It essentially is a macroblock processor and produces the decoded outputs for a macroblock after two macroblock pipeline delays. When it is no longer supplied with macroblock inputs then the pipeline stalls and does not flush out. Thus two macroblocks from a new picture are needed to produce the decoded outputs from the last two macroblocks in a previous picture. YUV Output Port Decoded pixel data is presented at the YUV port in standard macroblock format at quarter SYSCLK frequency (6.75MHz max), and in the macroblock order presented at the input. Since the VP2615 always expects a complete picture's worth of GOB's and macroblocks ( unless Skip Picture is sent by the video de-mux ), then it will always produce a complete 5 5 Page http://www.mitelsemi.com North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 Asia/Paciﬁc Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever. Purchasers of products are also hereby notiﬁed that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or other intellectual property rights owned by Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their speciﬁcations, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speciﬁc piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in signiﬁcant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s conditions of sale which are available on request. M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation Mitel Semiconductor is an ISO 9001 Registered Company Copyright 1999 MITEL Corporation All Rights Reserved Printed in CANADA TECHNICAL DOCUMENTATION - NOT FOR RESALE 11 Page

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