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VP2611CGGH1R の電気的特性と機能

VP2611CGGH1RのメーカーはMitel Networks Corporationです、この部品の機能は「H.261 Encoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 VP2611CGGH1R
部品説明 H.261 Encoder
メーカ Mitel Networks Corporation
ロゴ Mitel Networks Corporation ロゴ 




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VP2611CGGH1R Datasheet, VP2611CGGH1R PDF,ピン配置, 機能
Supersedes June 1996 edition, DS3487 - 4.0
VP2611
VP2611
H.261 Encoder
DS3487 - 4.1 December 1998
FEATURES
s Fully integrated H261 video encoder
s Up to full CIF resolution and 30 Hz frame rates
s Inputs YUV data in 8 x 8 sub block format
s Outputs run length coded coefficients
s On chip motion vector estimator with +/-7 pixel search
window
s Addresses and control generated internally for DRAM
frame store
s QFP package
ASSOCIATED PRODUCTS
s VP510 Colour Space Converter
s VP520S CIF/QCIF Converter
s VP2612 Video Multiplexer
s VP2614 Video Demultiplexer
s VP2615 H.261 Decoder
DESCRIPTION
The VP2611 Video Compression Source Coder forms part
of a chip set used in video conferencing, video telephony and
multimedia applications. It produces data which conforms to
the H261 standard for video compression with rates between
64K and 2M bits per second. With a 27 MHz clock the device
will accept data produced to full CIF resolution at 30 Hz frame
rates. The pipeline latency through the device is only 3 macro
block periods.
The VP2611 contains all the elements necessary for the
compression algorithm. It incorporates a Motion Vector Esti-
mator which performs a +/- 7 pixel search. The decision to use
inter or intra frame compression is made by the device, and the
selected data blocks are read from the frame store. New or
difference data is then passed through a Discrete Cosine
Transformer and quantized. Data from the quantizer is also
inverse quantized and passed through an Inverse Discrete
Cosine Transformer. This re-constructed data is then written
to the frame store for use in the next frame period.This frame
store is managed by an internal DRAM controller, and no
external logic is needed.
The input data must be in YUV space, and must also
conform to the six sub blocks per macro block format defined
by H261. Any conversion from RGB format is performed by
the VP510 Colour Space Converter. Any reduction in spatial
resolution, down to CIF or QCIF requirements, is done by the
VP520 Three Channel Video Filter.
The quantized data is zig-zag scanned and run length
coded before being output, together with block information
and motion vectors.
R VP510
G COLOUR SPACE
CONVERTER
B
NTSC
PAL
COMP VIDEO
DECODER
VIDEO
SYNC
USER
INTERFACE
Y
Cr/Cb
VP520
3 CHANNEL
VIDEO FILTER
REQYUV
FRMIN
MBLK'S
ADDR
DATA
CIF FRAME
STORE
16 X128K
SYSTEM
CONTROLLER
VP2611
RLC DATA
INTEGRATED
VIDEO ENCODER FLAGS
CIF FRAME
STORE
16X128K
CCIR601 RESOLUTION
Y 720 X 288 Cr/Cb 360 x 288
Y 720 X 240 Cr/Cb 360 x 240
NTSC
PAL
CIF RESOLUTION
Y 352 X 288
Cr/Cb 176 x 144
VP2612
VIDEO
MULTIPLEXER
TX BUFFER
32K X 8
H261
BIT
STREAM
64kb to 2Mb/s
Fig 1 : Typical Video Conferencing Transmission System
1

1 Page





VP2611CGGH1R pdf, ピン配列
VP2611
OPERATION OF MAJOR BLOCKS
Motion Vector Estimator
The motion estimator calculates the mean absolute error
( MAE ) for each possible position of the combined luminance
block in a search window from the previous frame. The
combined luminance block consists of 16 x 16 pixels, and in
the search window this is displaced between -7 to +7 vertically,
and -8 to +7 horizontally. The two lsb's of each pixel are
discarded and the MAE value is contained within 14 bits.
The minimum MAE value, representing the best match
between the previous and current block, is passed to the
motion compensation decision block, together with the posi-
tion of this best fit in the search window. The zero displace-
ment MAE value is also passed to this block, which then
decides whether the best fit is sufficiently better than the zero
displacement fit. It uses the characteristic shown in Figure 3,
where the 14 bit MAE is a Hex value. In the area to the right
of the line all points defined by the two MAE values will cause
motion compensation to be applied. In this case the best fit
MAE value is used by the inter/intra decision processor,
otherwise the zero displacement value is used.
Inter/Intra Decision Processor
The MAE value passed by the motion compensation
decision block is compared to the simplified variance of the
current block. This simplified variance is calculated by sum-
ming the moduli of the differences between each luminance
pixel and the mean luminance value over the whole macrob-
lock. Eight bit pixels are used, and the variance value is
expressed in 14 bits by discarding the two lsb's from the actual
16 bit result. It can then be directly compared to the 14 bit MAE
value.
If the MAE value is below a user defined threshold inter
mode coding is always selected. The default threshold is 3, on
a scale from 0 to 255 using the 8 msb's from the 14 bit value.
Above this threshold inter mode is only selected if the variance
of the current block is greater than or equal to the MAE value
in use.
In order to avoid gradual picture degredation, every 61st
Macroblock input to the VP2611 is coded in intra mode
regardless of the above decision. As 61 is a prime number, this
will ensure that each macroblock will be transmitted in intra
mode at least once in every 61 transmissions. If FIX MAC-
ROBLOCK or SKIP PICTURE is invoked this `Force Intra'
180
140 MC Off x = 1.125y
100
CO AB
80
5F
40
20
MC On
40 80 CO 100 140 180
Zero Movement Absolute Error in Hex
Fig 3 : MC Decision Slope
counter will be disabled.
The user may overide the internal Inter/Intra decision at
any time using the CBUS control port. A user generated
forced inter mode will overide an internally generated `Force
Intra'.
Low Pass Filter
The macroblock selected from the previous frame in
motion compensated inter mode coding, will be filtered before
it is subtracted from the current block. This decision can be
overidden externally by the system controller. The Filter uses
a simple [ 1 2 1 ] characteristic in both vertical and horizontal
dimensions as specified in H.261 on the macroblock boundaries
[010] is used.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
t RAC
t CAC
t RP
t CP
t RAS
t CAS
t REF
Access time from RAS
Access time from CAS
RAS precharge time
CAS precharge time
RAS pulse width
CAS pulse width
Time to refresh 256 rows
-
-
50ns or under
15ns or under
90ns or under
50ns or under
-
105ns or under
25ns or under
-
-
-
-
0.25ms or over
N.B. All times are quoted assuming 27MHz operation. For lower clock
frequencies increase the above values proportionately.
Table 1 : External DRAM timing requirements
3


3Pages


VP2611CGGH1R 電子部品, 半導体
VP2611
DBUS Output Port
The DBUS port is used to pass data and control informa-
tion directly to the VP2612 Video Multiplexer. The type of data
on the output pins is identified by the DMODE 3:0 outputs,
using the codes shown in Table 2. An output strobe is also
produced ( DCLK ) which always goes high one system clock
period after the data defined by DMODE 3:0 becomes valid.
This edge is used to strobe the data into the Video Multiplexer,
and thus the data set up time is always one SYSCLK period
minus differential output delays.
The number of SYSCLK periods during which data re-
mains valid is dependent on the type of data, and DCLK
remains high for this same period. It goes low as the result of
the same SYSCLK rising edge which produces a change in
DMODE 3:0. The output delays with respect to SYSCLK are
illustrated in Figure 8, and Figure 9 shows a typical output
sequence during which DCLK remains high for several cycles
as the sub-block number ( code 7 ) is produced. During a Wait
State
( code 15 ) no DCLK transitions are produced. The actual
sequence of output events which occur for each macroblock,
and the duration of each event, are illustrated in Figure 7.
The output events are defined in more detail below;
Control Decisions : This byte shows which control decisions
have been taken for the forthcoming macroblock. DBUS0
will be high if a Fixed Macroblock (FIX MB) was enforced
i.e. no new data will be transmitted this macroblock.
DBUS1 indicates whether Inter (high) or Intra (low) coding
was used for the macroblock. DBUS2 will be high if the
macroblock was filtered, and DBUS3 will be high if motion
compensation was used. DBUS5 will be high if the current
frame is being coded in FAST UPDATE mode. In this
mode the complete frame will be intra coded. DBUS6 will
be high if the current frame is a SKIP FRAME i.e. not being
coded - so no coefficients will be transmitted. DBUS4 and
DBUS7 are not used.
DMODE3:0
FUNCTION
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
GOB Number
MB Number
Control Decisions
Quant Value
Horizontal MV
Vertical MV
Coded Blk Pattern
Sub-Block No
Zero Run Count
RLC Coefficient
Not used
Not used
Not used
Not used
Not used
Wait State
Table 2 : DBUS Functions
6
START MB
WAIT
(2 cycles)
IS IT
A DUMMY
BLOCK?
no
CONTROL
yes
(2 cycles)
GOB
(2 cycles)
MB
CBP
(2 cycles)
(2 cycles)
QUANT
(2 cycles)
HORZ MV (2 cycles)
VERT MV (2 cycles)
ARE
ANY BLOCKS
CODED?
no
yes
WAIT
(32 cycles)
SUB BLK NO (15 cycles)
RUN LENGTH (2 cycles)
MAGNITUDE (2 cycles)
WAIT
(1 cycle)
ARE
ALL COEFFS
no O/P?
yes
WAIT
(wait variable time to make total
time since start of sub-block up
to 335 cycles)
no
ARE
ALL BLOCKS
O/P?
yes
WAIT
(variable cycles)
END MB
Fig 7 : DBUS Port Flow Chart

6 Page



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部品番号部品説明メーカ
VP2611CGGH1R

H.261 Encoder

Mitel Networks Corporation
Mitel Networks Corporation


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