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VP0550 の電気的特性と機能

VP0550のメーカーはSupertex Incです、この部品の機能は「P-Channel Enhancement-Mode Vertical DMOS FET」です。


製品の詳細 ( Datasheet PDF )

部品番号 VP0550
部品説明 P-Channel Enhancement-Mode Vertical DMOS FET
メーカ Supertex Inc
ロゴ Supertex  Inc ロゴ 




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VP0550 Datasheet, VP0550 PDF,ピン配置, 機能
Supertex inc.
VP0550
P-Channel Enhancement-Mode
Vertical DMOS FETs
Features
Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
High input impedance and high gain
Excellent thermal stability
Integral source-to-drain diode
Applications
Motor controls
Converters
Amplifiers
Switches
Power supply circuits
Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
General Description
The Supertex VP0550 is an enhancement-mode (normally-
off) transistor that utilizes a vertical DMOS structure and
Supertex’s well-proven silicon-gate manufacturing process.
This combination produces a device with the power handling
capabilities of bipolar transistors, and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free from
thermal runaway and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Ordering Information
Device
Package
TO-92
NW
(Die in wafer form)
Wafer / Die Options
NJ
(Die on adhesive tape)
VP0550
VP0550N3-G
VP1550NW
VP1550NJ
For packaged products, -G indicates package is RoHS compliant (‘Green’). Devices in Wafer / Die form are RoHS compliant (‘Green’).
Refer to Die Specification VF15 for layout and dimensions.
ND
(Die in waffle pack)
VP1550ND
Product Summary
Pin Configuration
Device
VP0550N3-G
BVDSS/BVDGS
(V)
-500
RDS(ON)
(max)
(Ω)
125
ID(ON)
(min)
(mA)
-100
SOURCE
DRAIN
Absolute Maximum Ratings
Parameter
Value
GATE
TO-92 (N3)
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature
-55°C to +150°C
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Product Marking
SiVP YY = Year Sealed
0 5 5 0 WW = Week Sealed
YYWW
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92 (N3)
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com

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VP0550 pdf, ピン配列
VP0550
Typical Performance Curves
Output Characteristics
-0.5
-0.4
-0.3
-0.2
-0.1
0
0
VGS = -10V
-8V
-7V
-6V
-5V
-10 -20 -30 -40
VDS (volts)
-50
Transconductance vs. Drain Current
100 VDS = -25V
TA = -55OC
80
25OC
60
150OC
40
20
0
0
-0.05
-0.10
-0.15
-0.20
-0.25
ID (amperes)
Maximum Rated Safe Operating Area
-1.0
-0.1
TO-92(DC)
-0.01
TC = 25OC
-0.001
-1
-10
-100
VDS (volts)
-1000
Saturation Characteristics
-100
VGS = -10V
-80 -8V -6V
-5V
-60
-4V
-40
-20
0 0 -2 -4 -6 -8 -10
VDS (volts)
Power Dissipation vs. Case Temperature
2.0
1.0
0
0
25
50
75
100 125
150
TC (OC)
Thermal Response Characteristics
1.0
0.8
0.6
0.4
0.2
0
0.001
0.01 0.1
tP (seconds)
PD = 1.0W
TC = 25OC
1.0 10
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
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部品番号部品説明メーカ
VP0550

P-Channel Enhancement-Mode Vertical DMOS FET

Supertex  Inc
Supertex Inc


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