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PDF VN16218 Data sheet ( Hoja de datos )
| Número de pieza | VN16218 | |
| Descripción | 2.5 Gigabit SERDES Transceiver | |
| Fabricantes | Vaishali Semiconductor | |
| Logotipo |  |
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Advance Information
VN16218
2.5 Gigabit SERDES Transceiver
Applications
•= Fast serial backplane transceiver
•= High-speed point-to-point links
General Description
The VN16218 is a low power single chip, 2.5GBd transceiver. It provides a 2.5GBd serial link interface in
the physical layer and includes a Serialize/Deserialize (SERDES) capability. Other functions include clock
generation, clock data recovery, and word synchronization. In addition, an internal loopback function is
provided for system debugging.
The VN16218 is ideal for 2.5 Gigabit, serial backplane and proprietary point-to-point applications. The
device supports both fiber-optic and copper media.
The transmitter section of the VN16218 accepts 20-bit wide TTL data and latches it on the rising edge of the
incoming Transmit Byte Clock (TBC) and serializes the data onto the TX± differential outputs, at a baud rate
that is twenty times the TBC frequency. The data is converted to a high-speed serial data stream. The
transmit PLL locks to the 125 MHz TBC. This clock is then multiplied by 20 to supply a 2.5 GHz serial clock
for parallel-to-serial conversion. The high-speed serial outputs can interface directly with copper cables or
PCB traces. Where optical transmission is required, the outputs can connect to a separate optical module.
When copper lines are the medium, equalization is available for improved performance.
The receiver section of the VN16218 accepts a serial data stream of 2.5 GBd and recovers 20 bit parallel
data. The receiver PLL locks on to the incoming serial signal and recovers the high-speed incoming clock
and data. The serial data is converted back into 20-bit parallel data format. Byte alignment is accomplished
by optional recognition of the K28.5+ comma character.
The recovered parallel data is sent to CMOS outputs, together with two 125 MHz clocks, RBC and RBCN,
that are 180 degrees out of phase from each other.
Features
•= 20-bit wide parallel Tx, Rx busses
•= 20-bit LVTTL interface for transmit and
receive data at 125 MHz
•= 125 MHz complementary receive and
byte clocks
•= Low Power Consumption
•= ESD rating >2000V (Human Body Model)
or >200V (Machine Model)
•= Parallel loopback mode
•= Available in 14 mm x 14 mm
LQFP package
•= Differential PECL serial output
•= I/O power supply 3.3V
•= Core power supply 1.8 V
2001-11-09
Page 1
MDSN-0003-00
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
1 page  
VN16218
Advance Information
Equalizer
When EQEN is HIGH, the equalizer at the receiver is enabled, in order to correct for the frequency response
of the cable or other system components. The equalizer compensates for distortion introduced by the cable,
in order to maintain a low bit-error rate.
Input Latch
The transmitter accepts 20 bits wide single-ended parallel input T[0:19]. The TBC provided by the sender of
the transmit data is used as the transmit byte clock. The T[0:19] and TBC signals must be aligned as
shown in Figure 5. The T[0:19] data is latched on the rising edge of TBC.
Clock Recovery
When EWR is LOW, the VN16218 accepts differential high-speed inputs on the RX+ and RX- pins, extracts
the clock and retimes the data. The serial bit stream should be encoded in a Fibre Channel compatible
8B/10B, or equivalent format, in order to accomplish DC-balance and limited run length. Clock recovery
circuitry is self-contained and does not require external components. The baud rate of the data stream to be
recovered should be within 200 ppm of twenty times the TBC frequency. This allows oscillators at either
end of the link to be 125 MHz ± 100ppm.
Deserializer (Serial-to-Parallel Converter)
The re-timed serial bit stream is converted into two 10-bit parallel output characters. The VN16218 provides
a TTL recovered clock (RBC) at one-twentieth the serial baud rate. This is accomplished by dividing down
the high-speed clock that is phase locked to the serial data. The serial data is re-timed by the internal high-
speed clock and deserialized. Parallel data results, and is captured by the adjoining protocol logic on the
rising edge of RBC
Word Alignment
The VN16218 has 7-bit Fibre Channel comma character recognition, and data word alignment. Word
synchronization (with EN_CD HIGH), causes the VN16218 to constantly search the serial data for the
presence of the Fibre Channel ‘comma’ character. This pattern is ‘0011111XX’: the leading zero
corresponds to the first bit received. The comma sequence occurs only within special characters (K28.1,
K28.5 and K28.7) that are defined specifically for synchronization in Fibre Channel systems.
Improper alignment condition of the comma character is defined as;
1. The comma is not aligned within the 10 bit transmission character such that T0…T6 = ‘0011111’
2. The comma straddles the boundary between two 10-bit transmission characters.
When EN_CD is HIGH and an improperly aligned comma is encountered, the internal data is shifted so that
the comma character is aligned properly in R0:6, as shown in Table 2. The result is proper character and
word alignment. When an improperly aligned comma pattern causes changes in parallel data alignment,
some data that would have been presented at the parallel output port may be lost. However, the
synchronization character and subsequent data will be sent correctly and properly aligned. With EN_CD
LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern.
A ‘comma’ character drives COM_DET HIGH to notify the user that realignment of the parallel data field
may have occurred. The COM_DET pulse occurs simultaneously with the ‘comma’ character and has a
duration equal to that of the data. The COM_DET pulse is timed so that it is captured by the adjoining
protocol logic, on the rising edge of RBC. Figures 3 and 4 show functional waveforms for synchronization.
Figure 3 illustrates the situation when a ‘comma’ character is detected, but no phase adjustment is
necessary. The position of the COM_DET pulse is shown in relation to the ‘comma’ character on R0:6.
Figure 4 illustrates the situation when K28.5 is detected, but is out- of-phase, and a change in the output
data alignment is required. It should be noted that up to three characters before the ‘comma’ character may
be corrupted by the realignment process.
2001-11-09
Page 5
MDSN-0003-00
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
5 Page 
VN16218
Figure 12. Mechanical Dimensions
80 Pin LQFP
Advance Information
A1 stand-off
A2 body thickness
L1 lead length
b lead width
c lead thickness
e lead pitch
All dimensions are in millimeters
D1/E1 b e L1 c A2 A1 A
14 0.3 0.65 1.0 0.127 1.4 0.1 1.5
Package follows JEDEC Standards
Ordering Information
Part Number Marking
Shipping/Packaging No. of Pins
VN16218L2 VN16218L2 Trays
80
Package
LQFP
Temperature
0°C to +70°C
2001-11-09
Page 11
MDSN-0003-00
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet VN16218.PDF ] | |
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