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PDF SK10E142PJ Data sheet ( Hoja de datos )
| Número de pieza | SK10E142PJ | |
| Descripción | 9-Bit Shift Register | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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SK10/100E142
HIGH-PER.ORMANCE PRODUCTS
Description
.eatures
9-Bit Shift Register
The SK10E/100E142 is a 9-bit shift register, designed
with byte-parity applications in mind. The E142 performs
serial/parallel in and serial/parallel out, shifting in one
direction. The nine inputs D0 – D8 accept parallel input
data, while S-IN accepts serial input data. The Qn outputs
do not need to be terminated for the shift operation to
function. To minimize noise and power, any Q output not
used should be left unterminated.
The SEL (Select) input pin is used to switch between the
two modes of operation – SHIFT and LOAD. The shift
direction is from bit 0 to bit 8. Input data is accepted by
the registers at set-up time before the posiitive going
edge of CLK1 or CLK2. Shifting is also accomplished
on the positive clock edge. A HIGH on the Master Reset
pin (MR) asynchronously resets all the registers to zero.
• 700 MHz Minimum Shift Frequency
• 9-Bit for Byte-Parity Applications
• Asynchronous Master Reset
• Dual Clocks
• Extended 100E VEE Range of –4.2 to –5.5V
• 75KΩ Internal Input Pulldown Resistors
• Fully Compatible with MC10E142 and
MC100E142
• Specified over Industrial Temperature Range:
–40oC to 85oC
• ESD Protection of >4000V
• Available in 28-pin PLCC Package
PIN Description
Pin Names
.unctional Block Diagram
S-IN
D0
D1
1
0
1
0
Q
D
Q0
Q
D
Q1
Pin
D0 - D8
S-IN
SEL
CLK1, CLK2
MR
Q0 - Q8
Pinout
.unction
Parallel Data Inputs
Serial Data Input
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
1
D2 0
1
D3 0
Q
D
Q2
Q
D
Q3
D8
SEL
CLK1
CLK2
MR
1
0
Q
D
Q8
Revision 1/.ebruary 14, 2001
25
MR 26
CLK1 27
CLK2 28
VEE 1
S-IN 2
D0 3
D1 4
5
24 23 22 21 20 19
18
17
28 Lead PLCC
(Top View)
16
15
14
13
12
6 7 8 9 10 11
Q7
Q6
VCC
Q5
VCC0
Q4
Q3
.unctions
SEL
L
H
1
Mode
Load
Shift
www.semtech.com
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