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PDF SII161A Data sheet ( Hoja de datos )
| Número de pieza | SII161A | |
| Descripción | SiI 161A PanelLink Receiver | |
| Fabricantes | ETC | |
| Logotipo |  |
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SiI 161A PanelLink® Receiver
Datasheet
March 2001
General Description
The SiI 161A receiver uses PanelLink Digital technology to support high
resolution displays up to UXGA. The SiI 161A receiver supports up to true
color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode. In
addition, the receiver data output is time staggered to reduce ground bounce
that affects EMI. Since all PanelLink products are designed on scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface, system designers can be assured that
the interface will be fixed through a number of technology and performance
generations.
PanelLink Digital technology simplifies PC and display interface design
by resolving many of the system level issues associated with high-speed
mixed signal design, providing the system designer with a digital interface
solution that is quicker to market and lower in cost.
Features
• Low Power: 3.3V core operation
• Time staggered data output for reduced ground
bounce
• Sync Detect: for Plug & Display “Hot Plugging”
• Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
• Compliant with DVI 1.0 (DVI is backwards
compatible with VESA® P&DTM and DFP)
§ Supports Dual-Link operation up to 330 Mega-
pixels/second
SiI 161A Pin Diagram
CONTROLS
GPO
EVEN 8-bits RED
QO2
QO3
QO4
QO5
QO6
QO7
OVCC
OGND
QO8
QO9
QO10
QO11
QO12
QO13
QO14
QO15
VCC
GND
QO16
QO17
QO18
QO19
QO20
QO21
QO22
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Silicon Image, Inc.
SiI 161A
100-Pin TQFP
(Top View)
DIFFERENTIALSIGNAL
25 QE13
24 QE12
23 QE11
22 QE10
21 QE9
20 QE8
19 OGND
18 OVCC
17 QE7
16 QE6
15 QE5
14 QE4
13 QE3
12 QE2
11 QE1
10 QE0
9 PDO
8 SCDT
7 STAG_OUT/SYNC
6 VCC
5 GND
4 PIXS/M_S
3 ST
2 PD
1 S_D
PLL
Subject to Change without Notice
1 page  
Silicon Image, Inc.
SiI 161A
SiI-DS-0009-D
AC Specifications
Under normal operating conditions unless otherwise specified.
Symbol Parameter
Conditions Min Typ Max Units
TDPS
TCCS
Intra-Pair (+ to -) Differential Input Skew1
Channel to Channel Differential Input Skew1
165MHz
165MHz
245 ps
4 ns
TIJIT Worst Case Differential Input Clock Jitter
tolerance2,3
65 MHz
112 MHz
465 ps
270 ps
165 MHz
182 ps
DLHT Low-to-High Transition Time: Data and Controls
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
CL = 10pF;
ST = 1
2.6 ns
CL = 5pF;
ST = 0
2.7 ns
Low-to-High Transition Time: Data and Controls
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
CL = 10pF;
ST = 1
2.4 ns
CL = 5pF;
ST = 0
3.0 ns
Low-to-High Transition Time: ODCK
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
CL = 10pF;
ST = 1
1.3 ns
CL = 5pF;
ST = 0
1.7 ns
Low-to-High Transition Time: ODCK
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
CL = 10pF;
ST = 1
1.4 ns
CL = 5pF;
ST = 0
1.7 ns
DHLT High-to-Low Transition Time: Data and Controls
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
CL = 10pF;
ST = 1
2.8 ns
CL = 5pF;
ST = 0
3.4 ns
High-to-Low Transition Time: Data and Controls
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
CL = 10pF;
ST = 1
2.3 ns
CL = 5pF;
ST = 0
3.3 ns
High-to-Low Transition Time: ODCK
(70 C, 82.5 MHz, 2-pixel/clock, PIXS=1)
CL = 10pF;
ST = 1
1.1 ns
CL = 5pF;
ST = 0
1.5 ns
High-to-Low Transition Time: ODCK
(70 C, 165 MHz, 1-pixel/clock, PIXS=0)
CL = 10pF;
ST = 1
1.2 ns
CL = 5pF;
ST = 0
1.5 ns
TSETUP
Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup
Time to ODCK falling edge (OCK_INV = 0) or to
CL = 10pF;
ST = 1
0.7
*0.7
ns
ODCK rising edge (OCK_INV = 1) at 165 MHz
*OCK_INV = 1
CL = 5pF;
ST = 0
0.7
*0.4
ns
THOLD
Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time CL = 10pF;
from ODCK falling edge, (OCK_INV = 0) or from
ST = 1
3.8
*3.8
ns
ODCK rising edge (OCK_INV = 1) at 165 MHz,
*OCK_INV = 0
CL = 5pF;
ST = 0
4.2
*3.8
ns
Notes:
1 Guaranteed by design.
2 Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
3 Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures.
4 Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
5 Measured when transmitter was powered down (see SiI /AN-0005 “PanelLink Basic Design/Application Guide,” Section 2.4).
Silicon Image, Inc.
5 Subject to Change without Notice
5 Page 
Silicon Image, Inc.
SiI 161A
SiI-DS-0009-D
Differential Signal Data Pins Description
Pin
Name
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
Pin # Type Description
90 Analog TMDS Low Voltage Differential Signal input data pairs.
91 Analog
85 Analog
86 Analog
80 Analog
81 Analog
RXC+ 93 Analog TMDS Low Voltage Differential Signal input data pairs.
RXC-
94 Analog
EXT_RES 96 Analog Impedance Matching Control. Resistor value should be approximately ten times the
characteristic impedance of the cable. In the common case of 50Ω transmission line,
an external 560Ω resistor must be connected between AVCC and this pin.
Reserved Pin Description
Pin Name Pin # Type Description
RESERVED 99 In Must be tied HIGH for normal operation.
Power and Ground Pins Description
Pin Name
Pin #
Type Description
VCC
6,38,67
Power Digital Core VCC, must be set to 3.3V.
GND
5,39,68
Ground Digital Core GND.
OVCC 18,29,43,57,78 Power Output VCC, must be set to 3.3V.
OGND 19,28,45,58,76 Ground Output GND.
AVCC
82,84,88,95 Power Analog VCC must be set to 3.3V.
AGND 79,83,87,89,92 Ground Analog GND.
PVCC
97 Power PLL Analog VCC must be set to 3.3V.
PGND
98 Ground PLL Analog GND.
Data D Q
ODCK
ODCK_INV
Silicon Image, Inc.
11
Subject to Change without Notice
11 Page | ||
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| PDF Descargar | [ Datasheet SII161A.PDF ] | |
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