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7013 の電気的特性と機能

7013のメーカーはAnalog Devicesです、この部品の機能は「CMOS TIA IS-54 Baseband Receive Port」です。


製品の詳細 ( Datasheet PDF )

部品番号 7013
部品説明 CMOS TIA IS-54 Baseband Receive Port
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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7013 Datasheet, 7013 PDF,ピン配置, 機能
a
CMOS
TIA IS-54 Baseband Receive Port
AD7013
FEATURES
Single +5 V Supply
Receive Channel
Differential or Single-Ended Analog Inputs
Auxiliary Set of Analog I & Q Inputs
Two Sigma-Delta A/D Converters
Choice of Two Digital FIR Filters
Root-Raised-Cosine Rx Filters, α = 0.35
Brick Wall FIR Rx Filters
On-Chip or User Rx Offset Calibration
ADC Sampling Vernier
Three Auxiliary DACs
On-Chip Voltage Reference
Low Active Power Dissipation, Typical 45 mW
Low Sleep Mode Power Dissipation, <50 µW
28-Pin SSOP
APPLICATIONS
American TIA Digital Cellular Telephony
American Analog Cellular Telephony
Digital Baseband Receivers
GENERAL DESCRIPTION
The AD7013 is a complete low power, CMOS, TIA IS-54 base-
band receive port with single +5 V power supply. The part is
designed to perform the baseband conversion of I and Q
waveforms in accordance with the American (TIA IS-54)
Digital Cellular Telephone system.
The receive path consists of two high performance sigma-delta
ADCs, each followed by a FIR digital filter. A primary and
auxiliary set of IQ differential analog inputs are provided,
where either can be selected as inputs to the sigma-delta
ADCs. Also, a choice of two frequency responses are available
for the receive FIR filters; a Root-Raised-Cosine filter for
digital mode or a brick wall response for analog mode.
Differential analog inputs are provided for both I and Q
channels. On-chip calibration logic is also provided to remove
either on-chip offsets or remove system offsets. A 16-bit serial
interface is provided, interfacing easily to most DSPs. The
receive path also provides a means to vary the sampling
instant, giving a resolution to 1/32 of a symbol interval.
The auxiliary section provides two 8-bit DACs and one 10-bit
DAC for functions such as automatic gain control (AGC),
automatic frequency control (AFC) and power amplifier
control.
As it is a necessity for all digital mobile systems to use the
lowest possible power, the device has receive and auxiliary
power down options. The AD7013 is housed in a space
efficient 28-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
DxCLK
DATA IN
FRAME IN
MODE1
FRAME OUT
Rx CLK
Rx DATA
Rx FRAME
MCLK
DGND VDD
AUX DAC1 AUX DAC2 AUX DAC3
FS ADJUST VAA AGND
SERIAL
INTERFACE
RECEIVE
CHANNEL
SERIAL
INTERFACE
10-BIT
AUX DAC
8-BIT
AUX DAC
8-BIT
AUX DAC
FULL-SCALE
ADJUST
LATCH
LATCH
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
LATCH
1.23V
REFERENCE
AD7013
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
OFFSET
ADJUST
ANALOG MODE
FIR DIGITAL FILTER
ROOT RAISED COSINE
FIR DIGITAL FILTER
∆Σ
MODULATOR
SWITCHED
CAP FILTER
MUX
AGND
AGND
BYPASS
IRx
IRx
AUX IRx
AUX IRx
QRx
QRx
AUX QRx
AUX QRx
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

1 Page





7013 pdf, ピン配列
AD7013
Parameter
AUXILIARY SECTION
AD7013A
Units
Test Conditions/Comments
Resolution
DC Accuracy
Integral
Differential
Zero Code Leakage
Gain Error
Output Full-Scale Current
Output Impedance4
Output Voltage Compliance
Coding
Power Down Option
AUX DAC1 AUX DAC2 AUX DAC3
10 8
8
Bits
±3
–1.5/+4
± 500
± 7.5
566
±1
±1
± 500
± 7.5
280
2
2.6
Binary
Yes
±1
±1
± 500
± 7.5
280
LSBs max
LSBs max
nA max
% max
µA
Mtyp
Volts max
AUX DAC2 & AUX DAC3 Guaranteed
Monotonic
RSET = 18 k
REFERENCE SPECIFICATIONS
VREF
Reference Accuracy
Reference Impedance
1.23
±5
20
Volts typ
% max
ktyp
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
VDD
IDD5
All Sections Active
ADCs Active Only
AUX DACs Active Only
10-Bit AUX DAC Active
All Sections Powered Down6
VDD–0.9
0.9
10
10
VDD–0.4
0.4
4.5/5.5
10.5
9
8.6
2.2
1.6
2
30
10
V min
V max
µA max
pF max
V min
V max
|IOUT| 40 µA
|IOUT| 1.6 mA
VMIN/VMAX
mA max
mA typ
mA max
mA max
mA max
mA max
µA typ
µA max
CR14 = CR15 = CR16 = CR17 = 1
MCLK = 6.2208 MHz; 80 pF
Load on DxCLK
CR14 = 1; CR15 = CR16 = CR17 = 0
MCLK = 6.2208 MHz; 80 pF
Load on DxCLK
CR14 = 0; CR15 = CR16 = CR17 = 1;
MCLK Inactive, MCLK = 0 V
CR14 = CR15 = CR16 = 0; CR17 = 1;
MCLK Inactive, MCLK = 0 V
CR14 = CR15 = CR16 = CR17 = 0
MCLK = 6.2208 MHz; 80 pF
Load on DxCLK
MCLK =100 kHz; 80 pF
Load on DxCLK
MCLK Inactive, MCLK = 0 V
NOTES
1Operating temperature ranges as follows: A version: –40°C to +85°C.
2SNR calculation includes noise and distortion components.
3See Terminology.
4Sampled tested only.
5Measured while the digital inputs are static and equal to 0 V or VDD.
6With all sections powered down, IDD is proportional to the capacitive load on DxCLK. For example, I DD is typically 1.7 mA with 80 pF load and 600 µA with
10 pF load.
Specifications subject to change without notice.
REV. A
–3–


3Pages


7013 電子部品, 半導体
AD7013
CONTROL SERIAL INTERFACE TIMING1
(VAA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V,
fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Limit at
TA = –40°C to +85°C
160
65
65
20
60
2t1
t1–20
t1–20
25
10
16t5
25
10
0
25
25
25
Units
ns min
ns min
ns min
ns min
ns max
ns
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
Description
MCLK Cycle Time
MCLK High Time
MCLK Low Time
MCLK Rising Edge to DxCLK Rising Edge Propagation Delay
DxCLK Cycle Time
DxCLK Minimum High Time
DxCLK Minimum Low Time
DxCLK Rising Edge to FRAME IN Setup Time
DxCLK Rising Edge to FRAME IN Hold Time
FRAME IN Cycle Time
DxCLK Rising Edge to DATA IN Setup Time
DxCLK Rising Edge to DATA IN Hold Time
FRAME IN Rising Edge to FRAME OUT Rising Edge Propagation Delay
MODE1 Low to FRAME OUT 3-STATE
MODE1 High to FRAME OUT Active
NOTE
1t14 is derived from the measured time taken by the FRAME OUT pin to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the
1.6mA IOL
MxCLK (I)
DxCLK (O)
t4
t8
FRAME IN (I)
DATA IN (I)
t13
FRAME OUT (O)
TO OUTPUT PIN
CL
50pF
200µA IOH
+2.1V
Figure 1. Load Circuit for Digital Outputs
t1 t2
t3
t5 t6
t9 t7
t10
t12
t11
DB9 DB8
DB1
DATA
DB0
A3 A0 S1 S0
ADDRESS
t14
3 – STATE
IGNORED
t15
MODE1 (I)
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT, MODE1 = LOGIC HIGH
Figure 2. 16-Bit Serial Interface for Writing to the AD7013 Internal Registers
–6– REV. A

6 Page



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