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74AC109SC の電気的特性と機能

74AC109SCのメーカーはFairchild Semiconductorです、この部品の機能は「Dual JK Positive Edge-Triggered Flip-Flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 74AC109SC
部品説明 Dual JK Positive Edge-Triggered Flip-Flop
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74AC109SC Datasheet, 74AC109SC PDF,ピン配置, 機能
74AC109, 74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
March 2007
tm
Features
ICC reduced by 50%
Outputs source/sink 24mA
ACT109 has TTL-compatible inputs
General Description
The AC/ACT109 consists of two high-speed completely
independent transition clocked JK flip-flops. The clocking
operation is independent of rise and fall times of the
clock waveform. The JK design allows operation as a
D-Type flip-flop (refer to AC/ACT74 data sheet) by
connecting the J and K inputs together.
Asynchronous Inputs:
– LOW input to SD (Set) sets Q to HIGH level
– LOW input to CD (Clear) sets Q to LOW level
– Clear and Set are independent of clock
– Simultaneous LOW on CD and SD makes both
Q and Q HIGH
Ordering Information
Order
Number
74AC109SC
74AC109SJ
74AC109MTC
Package
Number
M16A
M16D
MTC16
74ACT109SC
74AC109MTC
M16A
MTC16
74ACT109PC
N16E
Package Description
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16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
www.fairchildsemi.com

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74AC109SC pdf, ピン配列
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
IIK
VI
IOK
VO
IO
ICC or IGND
TSTG
TJ
Supply Voltage
DC Input Diode Current
VI = –0.5V
VI = VCC + 0.5V
DC Input Voltage
DC Output Diode Current
VO = –0.5V
VO = VCC + 0.5V
DC Output Voltage
DC Output Source or Sink Current
DC VCC or Ground Current per Output Pin
Storage Temperature
Junction Temperature
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to VCC + 0.5V
–20mA
+20mA
–0.5V to VCC + 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
VI
VO
TA
V / t
V / t
Parameter
Supply Voltage
AC
ACT
Input Voltage
Output Voltage
Operating Temperature
Minimum Input Edge Rate, AC Devices:
VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
0V to VCC
–40°C to +85°C
125mV/ns
125mV/ns
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
3
www.fairchildsemi.com


3Pages


74AC109SC 電子部品, 半導体
AC Electrical Characteristics for AC
Symbol
Parameter
fMAX Maximum Clock Frequency
tPLH Propagation Delay,
CPn to Qn or Qn
tPHL Propagation Delay,
CPn to Qn or Qn
tPLH Propagation Delay,
CDn or SDn to Qn or Qn
tPHL Propagation Delay,
CDn or SDn to Qn or Qn
VCC (V)(6)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
Min. Typ. Max. Min.
Max.
125 150
100
150 175
125
4.0 8.0 13.5
3.5
16.0
2.5 6.0 10.0
2.0
10.5
3.0 8.0 14.0
3.0
14.5
2.0 6.0 10.0
1.5
10.5
3.0 8.0 12.0
2.5
13.0
2.5 6.0 9.0
2.0
10.0
3.0 10.0 12.0
3.0
13.5
2.0 7.5 9.5
2.0
10.5
Units
MHz
ns
ns
ns
ns
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for AC
Symbol
Parameter
tS Setup Time, HIGH or LOW,
Jn or Kn to CPn
tH Hold Time, HIGH or LOW,
Jn or Kn to CPn
tW Pulse Width, CDn or SDn
tREC
Recovery Time,
CDn or SDn to CPn
VCC (V)(7)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C, TA = –40°C to +85°C,
CL = 50pF
CL = 50 pF
Typ.
Guaranteed Minimum
3.5 6.5
7.5
2.0 4.5
5.0
–1.5 0
0
–0.5 0.5
0.5
2.0 7.0
7.5
2.0 4.5
5.0
–2.5 0
0
–1.5 0
0
Units
ns
ns
ns
ns
Note:
7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
6
www.fairchildsemi.com

6 Page



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共有リンク

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部品番号部品説明メーカ
74AC109SC

Dual JK Positive Edge-Triggered Flip-Flop

Fairchild Semiconductor
Fairchild Semiconductor
74AC109SJ

Dual JK Positive Edge-Triggered Flip-Flop

Fairchild Semiconductor
Fairchild Semiconductor


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