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74AC02MTC の電気的特性と機能

74AC02MTCのメーカーはFairchild Semiconductorです、この部品の機能は「Quad 2-Input NOR Gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 74AC02MTC
部品説明 Quad 2-Input NOR Gate
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74AC02MTC Datasheet, 74AC02MTC PDF,ピン配置, 機能
www.DataSheet4U.com
November 1988
Revised February 2005
74AC0274ACT02
Quad 2-Input NOR Gate
General Description
The AC02/ACT02 contains four, 2-input NOR gates.
Features
s ICC reduced by 50% on 74AC02 only
s Outputs source/sink 24 mA
s ACT02 has TTL-compatible inputs
Ordering Codes:
Order Number
Package
Number
Package Description
74AC02SC
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC02SCX_NL
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC02SJ
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC02MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC02PC
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT02SC
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT02MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT02PC
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (PC not available in Tape and Reel.)
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
An, Bn
On
Description
Inputs
Outputs
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation DS009912
www.fairchildsemi.com

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74AC02MTC pdf, ピン配列
DC Electrical Characteristics for ACT
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA 25qC
TA 40qC to 85qC
(V) Typ
Guaranteed Limits
4.5 1.5 2.0
2.0
5.5 1.5 2.0
2.0
4.5 1.5 0.8
0.8
5.5 1.5 0.8
0.8
4.5 4.49 4.4
4.4
5.5 5.49 5.4
5.4
VOL Maximum LOW Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001 0.1
5.5 0.001 0.1
3.76
4.76
0.1
0.1
4.5 0.36
5.5 0.36
IIN Maximum Input
Leakage Current
5.5
r0.1
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 7)
Maximum Quiescent
Supply Current
5.5 0.6
5.5
5.5
5.5 4.0
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
0.44
0.44
r1.0
1.5
75
75
40.0
Units
Conditions
V VOUT 0.1V or
VCC  0.1V
V VOUT 0.1V or
VCC  0.1V
V IOUT 50 PA
VIN VIL or VIH
V IOH 24 mA
IOH 24 mA (Note 6)
V IOUT 50 PA
VIN VIL or VIH
V IOL 24 mA
IOL 24 mA (Note 6)
PA VI VCC, GND
mA VI VCC  2.1V
mA VOLD 1.65V Max
mA VOHD 3.85V Min
PA VIN VCC or GND
AC Electrical Characteristics for AC
Symbol
Parameter
tPLH Propagation Delay
tPHL Propagation Delay
Note 8: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
TA 25qC
CL 50 pF
Min Typ Max
1.5 5.0 7.5
1.5 4.0 6.0
1.5 5.0 7.5
1.5 4.5 6.5
TA 40qC to 85qC
CL 50 pF
Min Max
1.0 8.0
1.0 6.5
1.0 8.0
1.0 7.0
Units
ns
ns
AC Electrical Characteristics for ACT
Symbol
Parameter
tPLH Propagation Delay
tPHL Propagation Delay
Note 9: Voltage Range 5.0 is 5.0V r 0.5V
VCC
(V)
(Note 9)
5.0
5.0
TA 25qC
CL 50 pF
Min Typ Max
1.0 6.0 8.5
1.0 6.5 9.5
TA 40qC to 85qC
CL 50 pF
Min Max
1.0 9.0
1.0 10.0
Units
ns
ns
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
30.0
Units
pF
pF
Conditions
VCC OPEN
VCC 5.0V
3 www.fairchildsemi.com


3Pages


74AC02MTC 電子部品, 半導体
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
www.fairchildsemi.com
6

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部品番号部品説明メーカ
74AC02MTC

Quad 2-Input NOR Gate

Fairchild Semiconductor
Fairchild Semiconductor


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