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PDF 74ABT16652 Data sheet ( Hoja de datos )
| Número de pieza | 74ABT16652 | |
| Descripción | 16-Bit Transceivers and Registers with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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April 1993
Revised January 1999
74ABT16652
16-Bit Transceivers and Registers with 3-STATE Outputs
General Description
The ABT16652 consists of sixteen bus transceiver circuits
with D-type flip-flops, and control circuitry arranged for mul-
tiplexed transmission of data directly from the input bus or
from the internal registers. Each byte has separate control
inputs which can be shorted together for full 16-bit opera-
tion. Data on the A or B bus will be clocked into the regis-
ters as the appropriate clock pin goes to HIGH logic level.
Output Enable pins (OEAB, OEBA) are provided to control
the transceiver function.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s Separate control logic for each byte
s A and B output sink capability of 64 mA, source
capability of 32 mA
s Guaranteed output skew
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16652CSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16652CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Connection Diagram
Pin Names
A0–A16
B0–B16
CPABn, CPBAn
SABn, SBAn
OEABn, OEBAn
Descriptions
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Inputs
© 1999 Fairchild Semiconductor Corporation DS011599.prf
www.fairchildsemi.com
1 page  
DC Electrical Characteristics
(SSOP Package)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCC
CL = 50 pF, RL = 500Ω
VOLP
Quiet Output Maximum Dynamic VOL
0.7 1.2 V 5.0 TA = 25°C (Note 5)
VOLV
Quiet Output Minimum Dynamic VOL
−1.4
−1.0
V 5.0 TA = 25°C (Note 5)
VOHV
Minimum HIGH Level Dynamic Output Voltage 2.5
3.0
V 5.0 TA = 25° (Note 6)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.6
V 5.0 TA = 25°C (Note 7)
VILD Maximum LOW Level Dynamic Input Voltage
1.2 0.8 V 5.0 TA = 25°C (Note 7)
Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
AC Electrical Characteristics
(SSOP Package)
Symbol
Parameter
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
Clock to Bus
Propagation Delay
Bus to Bus
Propagation Delay
SBAn or SABn
to An to Bn
Enable Time
OEBAn or OEABn
to An or Bn
Disable Time
OEBAn or OEABn
to An or Bn
AC Operating Requirements
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
1.5 3.0 4.9
1.5 3.4 4.9
1.5 2.6 4.5
1.5 3.0 4.5
1.5 2.9 5.0
1.5 3.2 5.0
1.5 2.8 5.5
1.5 3.0 5.5
1.5 3.9 5.9
1.5 3.3 5.9
TA = −40°C to +85°C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
1.5 4.9
1.5 4.9
1.5 4.5
1.5 4.5
1.5 5.0
1.5 5.0
1.5 5.5
1.5 5.5
1.5 5.9
1.5 5.9
Units
ns
ns
ns
ns
ns
Symbol
Parameter
fmax
tS(H)
tS(L)
tH(H)
tH(L)
tW(H)
tW(L)
Max Clock Frequency
Setup Time, HIGH
or LOW Bus to Clock
Hold Time, HIGH
or LOW Bus to Clock
Pulse Width,
HIGH or LOW
TA = +25°C
VCC = +5.0V
CL = 50 pF
Min Typ Max
200
2.0
1.0
3.0
TA = −40°C to +85°C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
2.0
1.0
3.0
Units
MHz
ns
ns
ns
5 www.fairchildsemi.com
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74ABT16652.PDF ] | |
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