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74ABT16646 の電気的特性と機能

74ABT16646のメーカーはFairchild Semiconductorです、この部品の機能は「16-Bit Transceivers and Registers with 3-STATE Outputs」です。


製品の詳細 ( Datasheet PDF )

部品番号 74ABT16646
部品説明 16-Bit Transceivers and Registers with 3-STATE Outputs
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74ABT16646 Datasheet, 74ABT16646 PDF,ピン配置, 機能
October 1993
Revised November 1999
74ABT16646
16-Bit Transceivers and Registers with 3-STATE Outputs
General Description
The ABT16646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s A and B output sink capability of 64 mA, source
capability of 32 mA
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16646CSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300Wide
74ABT16646CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
A0A15
B0B15
CPABn, CPBAn
SABn, SBAn
OEn
DIR
Description
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
© 1999 Fairchild Semiconductor Corporation DS011644
www.fairchildsemi.com

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74ABT16646 pdf, ピン配列
Logic Diagram
3 www.fairchildsemi.com


3Pages


74ABT16646 電子部品, 半導体
Extended AC Electrical Characteristics
(SSOP Package)
TA = −40°C to +85°C
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = 4.5V5.5V
VCC = 4.5V5.5V
VCC = 4.5V5.5V
Symbol
Parameter
CL = 50 pF
8 Outputs Switching
CL = 250 pF
1 Output Switching
CL = 250 pF
8 Outputs Switching
Units
(Note 9)
(Note 10)
(Note 11)
Min Max Min Max Min Max
tPLH Propagation Delay
tPHL
Clock to Bus
1.5 5.8 2.0 7.5 2.5 10.0
ns
1.5 5.8 2.0 7.5 2.5 10.0
tPLH Propagation Delay
tPHL
Bus to Bus
1.5 6.5 2.0 7.0 2.5 9.5
ns
1.5 6.5 2.0 7.0 2.5 9.5
tPLH
tPHL
Progagation Delay
SBAn or SABn to An or Bn
1.5 6.0 2.0 7.5 2.5 10.0
ns
1.5 6.0 2.0 7.5 2.5 10.0
tPZH
tPZL
Output Enable Time
OEn to An or Bn
1.5 6.0 2.0 8.0 2.5 10.5
ns
1.5 6.0 2.0 8.0 2.5 10.5
tPHZ
tPLZ
Output Disable Time
OEn to An or Bn
1.5 6.0
1.5 6.0
(Note 12)
(Note 12)
ns
tPZH
tPZL
Output Enable Time
DIR to An or Bn
1.5 6.5 2.0 8.0 2.5 10.5
ns
1.5 6.5 2.0 8.0 2.5 10.5
tPHZ
tPLZ
Output Disable Time
DIR to An or Bn
1.5 6.5
1.5 6.5
(Note 12)
(Note 12)
ns
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 12: The 3-STATE delays are dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
www.fairchildsemi.com
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共有リンク

Link :


部品番号部品説明メーカ
74ABT16646

16-bit bus transceiver/register 3-State

NXP Semiconductors
NXP Semiconductors
74ABT16646

16-Bit Transceivers and Registers with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor


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