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74F114PCのメーカーはFairchild Semiconductorです、この部品の機能は「Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears」です。 |
部品番号 | 74F114PC |
| |
部品説明 | Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューと74F114PCダウンロード(pdfファイル)リンクがあります。 Total 6 pages
April 1988
Revised August 1999
74F114
Dual JK Negative Edge-Triggered Flip-Flop
with Common Clocks and Clears
General Description
The 74F114 contains two high-speed JK flip-flops with
common Clock and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to the transition time. The J and K inputs
can change when the clock is in either state without affect-
ing the flip-flop, provided that they are in the desired state
during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD
prevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on SD and CD force both Q and
Q HIGH.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of Clock
Simultaneous LOW on CD and SD
makes both Q and Q HIGH
Ordering Code:
Order Number Package Number
Package Description
74F114SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F114PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009474
www.fairchildsemi.com
1 Page Absolute Maximum Ratings(Note 1)
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Junction Temperature under Bias
−55°C to +150°C
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
3-STATE Output
−0.5V to VCC
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
VIH
VIL
VCD
VOH
VOL
IIH
IBVI
ICEX
VID
IOD
IIL
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output High
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
10% VCC
5% VCC
10% VCC
Min
2.0
2.5
2.7
4.75
IOS
ICCH
ICCL
Output Short-Circuit Current
Power Supply Current
Power Supply Current
−60
Typ
12.0
12.0
Max
Units
VCC
Conditions
V Recognized as a HIGH Signal
0.8 V
Recognized as a LOW Signal
−1.2 V Min IIN = −18 mA
V Min IOH = −1 mA
IOH = −1 mA
0.5 V Min IOL = 20 mA
5.0 µA Max VIN = 2.7V
7.0 µA Max VIN = 7.0V
50 µA Max VOUT = VCC
V 0.0 IID = 1.9 µA
All Other Pins Grounded
3.75
µA
0.0 VIOD = 150 mV
All Other Pins Grounded
−0.6
VIN = 0.5V (Jn, Kn)
−3.0
mA
Max
VIN = 0.5V (SDn)
−4.8
VIN = 0.5V (CP)
−6.0
VIN = 0.5V (CDn)
−150 mA Max VOUT = 0V
19.0 mA Max VO = HIGH
19.0 mA Max VO = LOW
3 www.fairchildsemi.com
3Pages Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
6
6 Page | |||
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部品番号 | 部品説明 | メーカ |
74F114PC | Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears | Fairchild Semiconductor |