54ABT16500W-QML Datasheet PDF - National Semiconductor
| Part Number | 54ABT16500W-QML | |
| Description | 18-Bit Universal Bus Transceivers with TRI-STATE Outputs | |
| Manufacturers | National Semiconductor | |
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July 1998
54ABT16500
18-Bit Universal Bus Transceivers with TRI-STATE®
Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transparent,
latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is
stored in the latch/flip-flop on the high-to-low transition of
CLKAB. Output-enable OEAB is active-high. When OEAB is
high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, and CLKBA. The output enables are complementary
(OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
n Combines D-Type latches and D-Type flip-flops for
operation in transparent, latched, or clocked mode
n Flow-through architecture optimizes PCB layout
n Guaranteed latch-up protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9687001
Ordering Code
Military
54ABT16500W-QML
Package
Number
WA56A
56-Lead Cerpack
Package Description
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100225
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof
www.national.com
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DC Electrical Characteristics
Symbol
Parameter
Min Max Units VCC
Conditions
CL = 50 pF; RL =
500Ω
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
1.1 V 5.0 TA = 25˚C (Note 7)
-1.7 V 5.0 TA = 25˚C (Note 7)
Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
AC Electrical Characteristics
Symbol
Parameter
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Maximum Clock Frequency
Propagation Delay
A or B to B or A
Propagation Delay
LEAB or LEBA to B or A
Propagation Delay
CLKAB or CLKBA to B or A
Propagation Delay
OEAB or OEBA to B or A
Propagation Delay
OEAB or OEBA to B or A
54ABT
TA = −55˚C to +125˚C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
150
1.0 6.5
1.0 7.0
1.0 7.0
1.0 7.8
1.0 7.5
1.0 8.0
1.0 6.3
1.0 6.5
1.0 7.2
1.0 6.8
Units
Fig.
No.
MHz
ns
ns
ns
ns
ns
Figure 4
Figure 4
Figure 4
Figure 6
Figure 6
AC Operating Requirements
Symbol
Parameter
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
Setup Time,
A to CLKAB
Hold Time,
A to CLKAB
Setup Time,
B to CLKBA
Hold Time,
B to CLKBA
Setup Time, A to LEAB
or B to LEBA, CLK High
Hold Time, A to LEAB
or B to LEBA, CLK High
Setup Time, A to LEAB
or B to LEBA, CLK Low
Hold Time, A to LEAB
or B to LEBA, CLK Low
Pulse Width,
LEAB or LEBA, High
54ABT
TA = −55˚C to +125˚C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
4.5
4.5
0
0
4.0
4.0
0
0
1.5
1.5
1.5
1.5
4.5
4.5
1.5
1.5
3.3
3.3
5
Units
Fig.
No.
ns Figure 7
ns Figure 7
ns Figure 7
ns Figure 7
ns Figure 7
Figure 7
ns
ns Figure 7
ns Figure 7
ns Figure 5
www.national.com
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 54ABT16500W-QML electronic component. |
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