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54ABT16500 の電気的特性と機能

54ABT16500のメーカーはNational Semiconductorです、この部品の機能は「18-Bit Universal Bus Transceivers with TRI-STATE Outputs」です。


製品の詳細 ( Datasheet PDF )

部品番号 54ABT16500
部品説明 18-Bit Universal Bus Transceivers with TRI-STATE Outputs
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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54ABT16500 Datasheet, 54ABT16500 PDF,ピン配置, 機能
July 1998
54ABT16500
18-Bit Universal Bus Transceivers with TRI-STATE®
Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transparent,
latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is
stored in the latch/flip-flop on the high-to-low transition of
CLKAB. Output-enable OEAB is active-high. When OEAB is
high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, and CLKBA. The output enables are complementary
(OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
n Combines D-Type latches and D-Type flip-flops for
operation in transparent, latched, or clocked mode
n Flow-through architecture optimizes PCB layout
n Guaranteed latch-up protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9687001
Ordering Code
Military
54ABT16500W-QML
Package
Number
WA56A
56-Lead Cerpack
Package Description
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100225
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof
www.national.com
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54ABT16500 pdf, ピン配列
Logic Diagram
DS100225-2
3
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof
www.national.com
3


3Pages


54ABT16500 電子部品, 半導体
AC Operating Requirements (Continued)
Symbol
Parameter
tw(H)
tw(L)
Pulse Width, CLKAB
or CLKBA, High or Low
54ABT
TA = −55˚C to +125˚C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
3.3
3.3
Capacitance
Symbol
Parameter
Typ
CIN
CI/O (Note 8)
Input Capacitance
Output Capacitance
5.0
11.0
Note 8: CI/O is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012.
Units
pF
pF
Units
Fig.
No.
ns Figure 5
Conditions, TA = 25˚C
VCC = 0.0V
VCC = 5.0V
www.national.com
6
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof
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6 Page



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共有リンク

Link :


部品番号部品説明メーカ
54ABT16500

18-Bit Universal Bus Transceivers with TRI-STATE Outputs

National Semiconductor
National Semiconductor
54ABT16500

54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE Outputs (Rev. A)

Texas Instruments
Texas Instruments
54ABT16500W-QML

18-Bit Universal Bus Transceivers with TRI-STATE Outputs

National Semiconductor
National Semiconductor


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