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DM74164 の電気的特性と機能

DM74164のメーカーはFairchild Semiconductorです、この部品の機能は「8-Bit Serial In/Parallel Out Shift Registers」です。


製品の詳細 ( Datasheet PDF )

部品番号 DM74164
部品説明 8-Bit Serial In/Parallel Out Shift Registers
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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DM74164 Datasheet, DM74164 PDF,ピン配置, 機能
September 1986
Revised February 2000
DM74164
8-Bit Serial In/Parallel Out Shift Registers
General Description
These 8-bit shift registers feature gated serial inputs and
an asynchronous clear. A LOW logic level at either serial
input inhibits entry of the new data, and resets the first flip-
flop to the LOW level at the next clock pulse, thus providing
complete control over incoming data. A HIGH logic level on
either input enables the other input, which will then deter-
mine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is HIGH or LOW, but only
information meeting the setup and hold time requirements
will be entered. Clocking occurs on the LOW-to-HIGH level
transition of the clock input. All inputs are diode-clamped to
minimize transmission-line effects.
Features
s Gated (enable/disable) serial inputs
s Fully buffered clock and serial inputs
s Asynchronous clear
s Typical clock frequency 36 MHz
s Typical power dissipation 185 mW
Ordering Code:
Order Number Package Number
Package Description
DM74164
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Inputs
Outputs
Clear Clock A B QA QB QH
L X XX L L … L
H L X X QA0 QB0 … QH0
H H H H QAn … QGn
H L X L QAn … QGn
H X L L QAn … QGn
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the
indicated steady-state input conditions were established.
QAn, QGn = The level of QA or QG before the most recent transition of the
clock; indicates a one-bit shift.
© 2000 Fairchild Semiconductor Corporation DS006552
www.fairchildsemi.com

1 Page





DM74164 pdf, ピン配列
Absolute Maximum Ratings(Note 1)
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range
65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
VCC Supply Voltage
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
IOH HIGH Level Output Current
IOL LOW Level Output Current
fCLK Clock Frequency (Note 2)
tW Pulse Width
Clock
(Note 2)
Clear
tSU Data Setup Time (Note 2)
tH Data Hold Time (Note 2)
TA Free Air Operating Temperature
Note 2: TA = 25°C and VCC = 5V.
Min
4.75
2
0
20
20
15
5
0
Nom
5
Max
5.25
0.8
0.4
8
25
70
Units
V
V
V
mA
mA
MHz
ns
ns
ns
°C
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min Max
(Note 3)
Units
VI Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
II Input Current @ Max Input Voltage
IIH HIGH Level Input Current
IIL LOW Level Input Current
IOS Short Circuit Output Current
ICC Supply Current
Note 3: All typicals are at VCC = 5V, TA = 25°C.
VCC = Min, II = −14 mA
VCC = Min, IOH = Max
VIL = Max, VIH = Min
VCC = Min, IOL = Max
VIH = Min, VIL = Max
VCC = Max, VI = 5.5V
VCC = Max, VI = 2.4V
VCC = Max, VI = 0.4V
VCC = Max (Note 4)
VCC = Max (Note 5)
1.5
V
2.4 3.2
V
0.2 0.4
V
1 mA
40 µA
1.6
mA
9
27.5
mA
37 54 mA
Note 4: Not more than one output should be shorted at a time.
Note 5: ICC is measured with all outputs OPEN, SERIAL inputs grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.5V, applied to the
CLEAR input.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
fMAX
tPLH
tPHL
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
From (Input)
To (Output)
Clock to Output
Clock to Output
Clear to Output
RL = 800
CL = 15 pF
CL = 50 pF
Min Max Min Max
25
27 30
32 37
36 42
Units
MHz
ns
ns
ns
3 www.fairchildsemi.com


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