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DM74125のメーカーはNational Semiconductorです、この部品の機能は「Quad TRI-STATE Buffers」です。 |
部品番号 | DM74125 |
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部品説明 | Quad TRI-STATE Buffers | ||
メーカ | National Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとDM74125ダウンロード(pdfファイル)リンクがあります。 Total 4 pages
June 1989
54125 DM54125 DM74125
Quad TRI-STATE Buffers
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function The outputs have
the TRI-STATE feature When enabled the outputs exhibit
the low impedance characteristics of a standard TTL output
with additional drive capability at the high Logic level to per-
mit the driving of bus lines without external pull-up resistors
When disabled both the output transistors are turned off
presenting a high-impedance state to the bus line Thus the
output will act neither as a significant load nor as a driver
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels the disable time
is shorter than the enable time of the outputs
Features
Y Alternate Military Aerospace device (54125) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram
Dual-In-Line Package
TL F 6540 – 1
Order Number 54125DMQB 54125FMQB DM54125J DM54125W or DM74125N
See NS Package Number J14A N14A or W14B
Function Table
YeA
Inputs
Output
AC
Y
LL
HL
XH
L
H
Hi-Z
H e High Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
Hi-Z e TRI-STATE (Outputs are disabled)
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 6540
RRD-B30M105 Printed in U S A
1 Page Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL e 400X
CL e 5 pF
CL e 50 pF
Min Max Min Max
Units
tPLH
Propagation Delay Time
Low to High Level Output
15 ns
tPHL
Propagation Delay Time
High to Low Level Output
18 ns
tPZH
Output Enable Time to
High Level Output
18 ns
tPZL Output Enable Time to
Low Level Output
25 ns
tPHZ
Output Disable Time from
High Level Output
8
ns
tPLZ Output Disable Time from
Low Level Output
14
ns
Physical Dimensions inches (millimeters)
14-Lead Ceramic Dual-In-Line Package (J)
Order Number 54125DMQB or DM54125J
NS Package Number J14A
3
3Pages | |||
ページ | 合計 : 4 ページ | ||
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PDF ダウンロード | [ DM74125 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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