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Datasheet FQA9P25 PDF ( 特性, スペック, ピン接続図 )

部品番号 FQA9P25
部品説明 250V P-Channel MOSFET
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 
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FQA9P25 Datasheet, FQA9P25 PDF,ピン配置, 機能
FQA9P25
250V P-Channel MOSFET
December 2000
QFETTM
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology is especially tailored to minimize
on-state resistance, provide superior switching
performance, and withstand a high energy pulse in the
avalanche and commutation modes. These devices are
well suited for high efficiency switching DC/DC converters.
Features
• -10.5A, -250V, RDS(on) = 0.62@VGS = -10 V
• Low gate charge ( typical 29 nC)
• Low Crss ( typical 27 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
G DS
TO-3P
FQA Series
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink
Thermal Resistance, Junction-to-Ambient
G!
S
!
▶▲
!
D
FQA9P25
-250
-10.5
-6.6
-42
± 30
650
-10.5
15
-5.5
150
1.2
-55 to +150
300
Typ
--
0.24
--
Max
0.83
--
40
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
©2000 Fairchild Semiconductor International
Rev. A2, December 2000

1 Page



FQA9P25 pdf, ピン配列
Typical Characteristics
V
GS
Top : -15.0 V
-10.0 V
-8.0 V
101 -7.0 V
-6.5 V
-6.0 V
Bottom : -5.5 V
100
10-1
10-1
Notes :
1. 250μs Pulse Test
2. T = 25
C
100 101
-V , Drain-Source Voltage [V]
DS
Figure 1. On-Region Characteristics
2.0
V = - 10V
GS
1.5
V = - 20V
GS
1.0
0.5
Note : T = 25
J
0.0
0 10 20 30 40
-I , Drain Current [A]
D
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
2400
2000
Ciss = Cgs + Cgd (Cds = shorted)
C =C +C
oss ds gd
Crss = Cgd
1600
1200
800
400
C Notes :
iss
1. VGS = 0 V
C 2. f = 1 MHz
oss
C
rss
0
10-1 100 101
-VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
101
100
10-1
2
150
25
-55
Notes :
1. VDS = -50V
2. 250μs Pulse Test
468
-VGS , Gate-Source Voltage [V]
10
Figure 2. Transfer Characteristics
101
100
10-1
0.0
15025
Notes :
1. V = 0V
GS
2. 250μs Pulse Test
0.5 1.0 1.5 2.0 2.5
-VSD , Source-Drain Voltage [V]
3.0
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
V = -50V
DS
10 V = -125V
DS
V = -200V
DS
8
6
4
2
Note : ID = -9.4 A
0
0 5 10 15 20 25 30 35
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A2, December 2000


3Pages


FQA9P25 電子部品, 半導体
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
I SD
Driver
RG
VGS
+
VDS
_
L
Compliment of DUT
(N-Channel)
• dv/dt controlled by RG
• ISD controlled by pulse period
VDD
VGS
( Driver )
I SD
( DUT )
VDS
( DUT )
D = --G--a--t-e--P--u--l-s-e---W---i-d-t-h--
Gate Pulse Period
10V
Body Diode Reverse Current
IRM
IFM , Body Diode Forward Current
VSD
di/dt
Body Diode
Forward Voltage Drop
Body Diode Recovery dv/dt
VDD
©2000 Fairchild Semiconductor International
Rev. A2, December 2000

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