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Datasheet FQA33N10L PDF ( 特性, スペック, ピン接続図 )

部品番号 FQA33N10L
部品説明 100V LOGIC N-Channel MOSFET
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 
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FQA33N10L Datasheet, FQA33N10L PDF,ピン配置, 機能
FQA33N10L
100V LOGIC N-Channel MOSFET
September 2000
QFETTM
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as high efficiency
switching DC/DC converters, and DC motor control.
Features
• 36A, 100V, RDS(on) = 0.052@VGS = 10 V
• Low gate charge ( typical 30 nC)
• Low Crss ( typical 70 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• 175°C maximum junction temperature rating
G DS
TO-3P
FQA Series
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink
Thermal Resistance, Junction-to-Ambient
D
!
"
!"
G!
"
"
!
S
FQA33N10L
100
36
25.5
144
± 20
430
36
16.3
6.0
163
1.09
-55 to +175
300
Typ
--
0.24
--
Max
0.92
--
40
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
©2000 Fairchild Semiconductor International
Rev. A, September 2000

1 Page



FQA33N10L pdf, ピン配列
Typical Characteristics
102 Top :
VGS
10.0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
101
100
10-1
Notes :
1. 250μs Pulse Test
2. TC = 25
100
V , Drain-Source Voltage [V]
DS
101
Figure 1. On-Region Characteristics
0.20
0.16
V = 5V
GS
0.12
V = 10V
GS
0.08
0.04
0.00
0
Note : T = 25
J
30 60 90
ID, Drain Current [A]
120
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
3600
3000
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
2400
1800
1200
600
C
iss
C
oss
Crss
Notes :
1. VGS = 0 V
2. f = 1 MHz
0
10-1 100 101
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2000 Fairchild Semiconductor International
102
101 175
25
100
10-1
0
-55
Notes :
1. VDS = 30V
2. 250μs Pulse Test
2468
VGS, Gate-Source Voltage [V]
10
Figure 2. Transfer Characteristics
102
101
100
10-1
0.2
175
0.4
25
Notes :
1. V = 0V
GS
2. 250μs Pulse Test
0.6 0.8 1.0 1.2 1.4 1.6 1.8
VSD, Source-Drain voltage [V]
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
V = 50V
DS
8
V = 80V
DS
6
4
2
Note : ID = 33A
0
0 10 20 30 40 50
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A, September 2000


3Pages


FQA33N10L 電子部品, 半導体
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
Same Type
as DUT
• dv/dt controlled by RG
• ISD controlled by pulse period
VDD
VGS
( Driver )
I SD
( DUT )
VDS
( DUT )
D
=
--G--a--t-e--P--u--l-s-e---W---i-d-t-h--
Gate Pulse Period
10V
IFM , Body Diode Forward Current
di/dt
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VSD
Body Diode
Forward Voltage Drop
VDD
©2000 Fairchild Semiconductor International
Rev. A, September 2000

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