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FDC37C93のメーカーはSMSC Corporationです、この部品の機能は「Plug and Play Compatible Ultra I/O Controller with Soft Power Management」です。 |
部品番号 | FDC37C93 |
| |
部品説明 | Plug and Play Compatible Ultra I/O Controller with Soft Power Management | ||
メーカ | SMSC Corporation | ||
ロゴ | |||
このページの下部にプレビューとFDC37C93ダウンロード(pdfファイル)リンクがあります。 Total 30 pages
FDC37C93xAPM
ADVANCE INFORMATION
Plug and Play Compatible Ultra I/O™ Controller
with Soft Power Management
FEATURES
• 5 Volt Operation
• ISA Plug-and-Play Standard (Version 1.0a)
Compatible Register Set
• Soft Power Management, SMI Support
• ACPI/Legacy Support
- SCI/SMI Support
- Power Management Timer
- Power Button Override Event
- Either Edge Triggered Interrupts
• ACCESS.bus Support
• 8042 Keyboard Controller
- 2K Program ROM
- 256 Bytes Data RAM
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Timer/Counter
- Port 92 Support
- Fast Gate A20 and Hardware Keyboard
Reset
• Real Time Clock
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format
- 1 µA Standby Current (typ)
• Intelligent Auto Power Management
• 2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Four DMA Options
- Licensed CMOS 765B Floppy Disk
Controller
- Advanced Digital Data Separator
- Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
- Game Port Select Logic
- Supports Two Floppy Drives Directly
- 24mA AT Bus Drivers
- Low Power CMOS Design
• Licensed CMOS 765B Floppy Disk
Controller Core
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun
Conditions
- 48mA Drivers and Schmitt Trigger Inputs
- DMA Enable Logic
- Data Rate and Drive Control Registers
• Enhanced Digital Data Separator
- Low Cost Implementation
- No Filter Components Required
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
• Serial Ports
- Relocatable to 480 Different Addresses
1 Page - 13 IRQ Options
- Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte
FIFOs
- Programmable Baud Rate Generator
- Modem Control Circuitry Including 230K
and 460K Baud
- IrDA, HP-SIR, ASK-IR Support
• IDE Interface
- Relocatable to 480 Different Addresses
- 13 IRQ Options (IRQ Steering through
Chip)
- Two Channel/Four Drive Support
- On-Chip Decode and Select Logic
Compatible with IBM PC/XT® and
PC/AT® Embedded Hard Disk Drives
• Serial EEPROM Interface
• Multi-Mode™ Parallel Port with ChiProtect™
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Four DMA Options
- Standard Mode
- IBM PC/XT, PC/AT, and PS/2™
Compatible Bidirectional ParallelPort
- Enhanced Mode
- Enhanced Parallel Port (EPP)
Compatible - EPP 1.7 and EPP 1.9
(IEEE 1284 Compliant)
- High Speed Mode
- Microsoft and Hewlett Packard
Extended Capabilities Port (ECP)
Compatible (IEEE 1284 Compliant)
- Incorporates ChiProtect™ Circuitry for
Protection Against Damage Due to
Printer Power-On
- 12 mA Output Drivers
• ISA Host Interface
• 16 Bit Address Qualification
• 160 Pin QFP Package
*Note:
The “X” in the Ultra I/O part number is a designator that changes
depending upon the particular BIOS used inside the specific chip.
“2” denotes AMI Keyboard BIOS/”5” denotes Phoenix Keyboard
BIOS.
3
3Pages DESCRIPTION OF PIN FUNCTIONS
PIN NO.
NAME
SYMBOL
PROCESSOR/HOST INTERFACE
72:79
41:52
System Data Bus
System Address Bus
SD[0:7]
SA[0:11]
53 Chip Select/SA12 (Active Low)(Note 1, 4)
70 Address Enable (DMA master has bus control)
nCS
AEN
90 I/O Channel Ready
IOCHRDY
80
67:61,
59:54
Reset Drive
Interrupt Requests [1,3:12,14,15]
(Polarity control for IRQ8)
RESET_DRV
IRQ[1,3:12,
14,15]
82,84, DMA Requests
86,88
DRQ[0:3]
81,83,
85,87
89
DMA Acknowledge
Terminal Count
nDACK[0:3]
TC
68 I/O Read
nIOR
69 I/O Write
35 High Speed Clock Out 24/48 MHz
nIOW
HCLK
36 16 MHz Out
16CLK
22 14.318 MHz Clock Input
37 14.318 MHz Clock Output 1
CLOCKI
CLKO1
38 14.318 MHz Clock Output 2
39 14.318 MHz Clock Output 3
CLKO2
CLKO3
POWER PINS
21, 60, +5V Supply Voltage
101, 125,
139
VCC
32
1, 8, 40,
71, 95,
123, 130
Trickle Voltage Input
Ground
VTR
GND
FDD INTERFACE
17 Read Disk Data
nRDATA
BUFFER
TYPE
I/O24
I
I
I
OD24
IS
024/OD24
(Note 0)
O24
I
I
I
I
O20
O8SR
ICLK
O16SR
O8SR
O8SR
IS
6
6 Page | |||
ページ | 合計 : 30 ページ | ||
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PDF ダウンロード | [ FDC37C93 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
FDC37C93 | Plug and Play Compatible Ultra I/O Controller with Soft Power Management | SMSC Corporation |
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FDC37C93XAPM | Plug and Play Compatible Ultra I/O Controller with Soft Power Management | SMSC Corporation |
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