DataSheet.jp

M-986-2A1PL の電気的特性と機能

M-986-2A1PLのメーカーはClare Inc.です、この部品の機能は「MF Transceiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 M-986-2A1PL
部品説明 MF Transceiver
メーカ Clare Inc.
ロゴ Clare  Inc. ロゴ 




このページの下部にプレビューとM-986-2A1PLダウンロード(pdfファイル)リンクがあります。

Total 13 pages

No Preview Available !

M-986-2A1PL Datasheet, M-986-2A1PL PDF,ピン配置, 機能
Features
Direct A-Law or µ-Law PCM digital input
2.048 Mb/s clocking
Operates with standard codecs for analog interfac-
ing
Microprocessor read/write interface
Binary or 2-of-6 data formats
Dual-channel
5 volt power
Applications
Test equipment
Trunk adapters
Paging terminals
Traffic recorders
PBXs
M-986-2A1
MF Transceiver
Description
The M-986-2A1 dual channel MF Transceiver con-
tains all the logic necessary to transmit and receive
(North American) CCITT Region 1 multifrequency
signals on one integrated circuit (IC).
Operating with a 20.48 MHz crystal, the M-986 is
capable of providing a direct digital interface to a m-
law or A-law encoded PCM digital input. Each channel
can be connected to an analog source using a coder-
decoder (codec) as shown in the Block Diagram
below.
The M-986 is configured and controlled through an
integral coprocessor port.
Ordering Information
Part #
M-986-2A1P
M-986-2A1PL
Description
40-pin plastic DIP
44-pin PLCC
Block Diagram
DS-M986-2A1
www.clare.com
1

1 Page





M-986-2A1PL pdf, ピン配列
M-986-2A1
Configuration
Bit 7 Bit 6
Bit 5
0 0 ECLK
ECLK
IOM
ENC1
KPL1
KPEN1
Channels 1 & 2
Channels 1 & 2
Channel 1
Channel 1
Channel 1
Bit 7
0
AMU
ENC2
KPL2
KPEN2
Bit 6 Bit 5
10
Channels 1 & 2
Channel 2
Channel 2
Channel 2
Configuration Byte 1
Bit 4 Bit 3 Bit 2
Bit 1
IOM ENCI KPL1 KPEN1
1 = External codec clock; 0 = Internal codec clock
1 = Binary input/output; 0 = 2-of-6 input/output
1 = Enable channel; 0 = Disable channel
1 = 55 ms detection time for KP; 0 = 30 ms detection time for KP
1 = Enable MF tone detection after KP detection;
0 = MF tone detection always on
Configuration Byte 2
Bit 4 Bit 3 Bit 2
Bit 1
AMU
ENC2
KPL2
KPEN2
1 = A-law Encoding, 0 = m-law Encoding
1 = Enable channel; 0 = Disable channel
1 = 55 ms detection time for KP; 0 = 30 ms detection time for KP
1 = Enable MF tone detection after KP detection;
0 = MF tone detection always
Bit 0
0
Bit 0
0
Initial Configuration: The configuration of the M-986-
2A1 immediately after a reset will be as follows:
channel disabled
2-of-6 input/output
external serial and serial frame clocks.
Also, the M-986-2A1 will place a 00 hex on the
coprocessor port to indicate to the host processor that
it is working.
Transmit Tone Command
The transmit tone command allows the host processor
to transmit any two of the 6 R1 MF frequencies. The
format of the command depends on whether the M-
986 is configured for binary format or 2-of-6 format.
Recieved Tone Detection
When a tone is detected by the M-986, the TBLF out-
put goes low, indicating reception of the tone to the
host processor. The host processor can determine
which tone was detected and which channel the tone
was detected on by reading data from the M-986
coprocessor port. The M-986 will return a single byte
indicating the tone received and the channel that the
tone was received on. The format of the returned byte
depends on whether the M-986 is configured for bina-
ry or 2-of-6 coding.
Coprocessor Port
Commands are written to the M-986 via the coproces-
sor port, and data indicating the received R1 MF tone
is read from the coprocessor port.
Writing to the Coprocessor Port: The following
sequence describes writing a command to the M-986.
(1) The WR signal is driven low by the host processor.
(2) The RBLE (receive buffer latch empty) signal tran-
sitions to a logic high level.
(3) Data is written from D7-D0 to the receive buffer
latch (D7-D0) when the WR signal goes high.
(4) The RBLE signal transitions to a logic low level
after the M-986 reads the data. This signals the host
processor that the receive buffer is empty.
Note: The RBLE should be low before writing to the
coprocessor.
Reading the Coprocessor Port: The following
sequence describes reading received tone informa-
tion from the coprocessor port.
(1) The TBLF (transmit buffer latch full) port pin on the
M-986 goes low indicating the reception of a tone.
(2) The host processor detects the low logic level on
the TBLF pin either by polling a connected port pin or
by an interrupt.
(3) The host processor drives the RD signal low.
(4) The TBLF (transmit buffer latch full) signal transi-
tion to a logic high level.
Rev. 3
www.clare.com
3


3Pages


M-986-2A1PL 電子部品, 半導体
M-986-2A1
Serial Port Timing
Parameter
td (CH-FR)
td (DX1-CL)
td (DX2-CL)
th (DX)
tsu (DR)
th (DR)
tc (SCLK)
tf (SCLK)
tr (SCLK)
tw (SCLKL)
tw (SCLKH)
tsu (FS)
Internal framing delay from SCLK rising edge
DX bit 1 valid before SCLK falling edge
DX bit 2 valid before SCLK falling edge
DX hold time after SCLK falling edge
DR setup time before SCLK falling edge
DR hold time after SCLK falling edge
Serial port clock cycle time
Serial port clock fall time
Serial port clock rise time
Serial port clock low-pulse duration*
Serial port clock high-pulse duration*
FSX/FSR setup time before SCLK falling edge
* The duty cycle of the serial port clock must be within 45% to 55%.
External Frequency Specifications
tC(MC)
tr(MC)
tf(MC)
Parameter
Master clock cycle time
Rise time master clock input
Pulse duration master clock
Recommended Operating Conditions
Parameter
VCC Supply voltage
VSS Supply voltage
VIH High-level input voltage
VIL Low-level input voltage
IOH High-level output current (all outputs)
IOL Low-level output current (all outputs)
TA Operating free-air temperature
All inputs except CLKIN
CLKIN
MC/PM
All inputs except MC/MP
MC/MP
Min
Nom
Max Unit
- - 70 ns
20 -
- ns
20 -
- ns
244 -
- ns
20 -
- ns
20 -
- ns
399
488.28
4770
ns
- - 30 ns
- - 30 ns
220
244.14
2500
ns
220
244.14
2500
ns
100 -
- ns
Min
48.818
-
20
Nom
48.828
5
-
Max
48.838
10
-
Unit
ns
ns
ns
Min Nom Max Unit
4.75 5 5.25 V
- 0 -V
2 - -V
3 - -V
2.2 -
-V
- - 0.8 V
- - 0.6 V
- - -300 µA
- - 2 mA
0 - 70 ˚C
6
www.clare.com
Rev. 3

6 Page



ページ 合計 : 13 ページ
 
PDF
ダウンロード
[ M-986-2A1PL データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
M-986-2A1P

MF Transceiver

Clare  Inc.
Clare Inc.
M-986-2A1PL

MF Transceiver

Clare  Inc.
Clare Inc.


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap