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M-88L70-01S の電気的特性と機能

M-88L70-01SのメーカーはClare Inc.です、この部品の機能は「3V DTMF Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 M-88L70-01S
部品説明 3V DTMF Receiver
メーカ Clare Inc.
ロゴ Clare  Inc. ロゴ 




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M-88L70-01S Datasheet, M-88L70-01S PDF,ピン配置, 機能
M-88L70
3V DTMF Receiver
Features
Operates between 2.7 and 3.6 volts
Low power consumption
Power-down mode
Inhibit mode
Central office quality and performance
Inexpensive 3.58 MHz time base
Adjustable acquisition and release times
Dial tone suppression
Functionally compatible with Clare’s M-8870
Applications
Telephone switch equipment
Mobile radio
Remote control
Paging systems
PCMCIA
Portable TAD
Remote data entry
Description
The M-88L70 monolithic DTMF receiver offers small size,
low power consumption and high performance, with 3 volt
operation. Its architecture consists of a bandsplit filter
section, which separates the high and low group tones,
followed by a digital counting section which verifies the
frequency and duration of the received tones before
passing the corresponding code to the output bus.
Ordering Information
Part #
M-88L70-01P
M-88L70-01S
M-88L70-01T
Description
18-pin plastic DIP
18-pin SOIC
18-pin SOIC, Tape and Reel
Figure 1 Pin Connections
The M-88L70 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-88L70 offers low
power consumption (18 mW max), precise data handling
and 3V operation. Its filter section uses switched capaci-
tor technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone pairs
into a 4-bit code. External component count is minimized
by provision of an on-chip differential input amplifier,
clock generator, and latched tri-state interface bus.
Minimal external components required include a low-cost
3.579545 MHz color burst crystal, a timing resistor, and a
timing capacitor.
Figure 2 Block Diagram
DS-M88L70-R1
www.clare.com
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M-88L70-01S pdf, ピン配列
M-88L70
ered a valid pause. This capability, together with the
ability to select the steering time constants externally,
allows the designer to tailor performance to meet a wide
variety of system requirements.
Figure 3 Basic Steering Circuit
Guard Time Adjustment
Where independent selection of receive and pause are
not required, the simple steering circuit of Figure 3 is
applicable. Component values are chosen according to
the formula:
tREC = tDP + tGTP
tGTP @ 0.67 RC
The value of tDP is a parameter of the device and tREC is
the minimum signal duration to be recognized by the
receiver. A value for C of 0.1 µF is recommended for
most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a tREC of
40 ms would be 300 K ohm. A typical circuit using this
steering configuration is shown in Figure 4. The timing
requirements for most telecommunication applications
are satisfied with this circuit. Different steering arrange-
ments may be used to select independently the guard
times for tone-present (tGTP) and tone-absent (tGTA). This
may be necessary to meet system specifications that
place both accept and reject limits on both tone duration
and interdigit pause.
Guard time adjustment also allows the designer to tailor
system parameters such as talkoff and noise immunity.
Increasing tREC improves talkoff performance, since it
reduces the probability that tones simulated by speech
will maintain signal condition long enough to be regis-
tered. On the other hand, a relatively short tREC with a
long tDO would be appropriate for extremely noisy envi-
ronments where fast acquisition time and immunity to
dropouts would be required. Design information for
guard time adjustment is shown in Figure 5.
Input Configuration
The input arrangement of the M-88L70 provides a dif-
ferential input operational amplifier as well as a bias
source (VREF) to bias the inputs at mid-rail. Provision is
made for connection of a feedback resistor to the op-
amp output (GS) for gain adjustment.
In a single-ended configuration, the input pins are con-
nected as shown in Figure 4 with the op-amp connect-
ed for unity gain and VREF biasing the input at 1/2VDD.
Figure 7 shows the differential configuration, which per-
mits gain adjustment with the feedback resistor R5.
Table 2 Tone Decoding
FLOW FHIGH Key OE INH ESt Q4 Q3 Q2 Q1
(ref.)
ANY ANY ANY L X H Z Z Z Z
697 1209 1 H X H 0 0 0 1
697 1336 2 H X H 0 0 1 0
697 1477 3 H X H 0 0 1 1
770 1209 4 H X H 0 1 0 0
770 1336 5 H X H 0 1 0 1
770 1477 6 H X H 0 1 1 0
852 1209 7 H X H 0 1 1 1
852 1336 8 H X H 1 0 0 0
852 1477 9 H X H 1 0 0 1
941 1336 0 H X H 1 0 1 0
941 1209 * H X H 1 0 1 1
941 1477 # H X H 1 1 0 0
697 1633 A H L H 1 1 0 1
770 1633 B H L H 1 1 1 0
852 1633 C H L H 1 1 1 1
941 1633 D H L H 0 0 0 0
697 1633
770 1633
852 1633
941 1633
A
B
C
D
HH
HH
HH
DH
L Undetected, the output
L code will remain the
L same as the previous
L detected code.
L = logic low, H = logic high, Z = high impedance, X = don’t care
Rev. 1 www.clare.com
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3Pages


M-88L70-01S 電子部品, 半導体
M-88L70
Figure 4 Single-Ended Input Configuration
Figure 5 Guard Time Adjustment
Figure 6 Timing Diagram
Explanation of Events
(A) Tone bursts detected, tone duration invalid, outputs not
updated.
(B) Tone #n detected, tone duration valid, tone decoded
and latched in outputs.
(C) End of tone #n detected, tone absent duration valid,
outputs remain latched until next valid tone.
(D) Outputs switched to high impedance state.
(E) Tone #n + 1 detected, tone duration valid, tone decod-
ed and latched in outputs (currently high impedance).
(F) Acceptable dropout of tone #n + 1, tone absent duration
invalid, outputs remain latched.
(G) End of tone #n + 1 detected, tone absent duration valid,
outputs remain latched until next valid tone.
Explanation of Symbols
VIN DTMF composite input signal.
ESt Early steering output. Indicates detection of
valid tone frequencies.
St/GT
Steering input/guard time output. Drives
external RC timing circuit.
Q1 - Q4 4-bit decoded tone output.
StD Delayed steering output. Indicates that valid
frequencies have been present/absent for
the required guard time, thus constituting a
valid signal.
OE Output enable (input). A low level shifts Q1 -
Q4 to its high impedance state.
tREC Maximum DTMF signal duration not detected
as valid.
tREC Minimum DTMF signal duration required for
valid recognition.
tID Minimum time between valid DTMF signals.
tDO Maximum allowable dropout during valid DTMF
signal.
tDP Time to detect the presence of valid DTMF
signals.
tDA Time to detect the absence of valid DTMF
signals.
tGTP Guard time, tone present.
tGTA Guard time, tone absent.
6
www.clare.com
Rev. 1

6 Page



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共有リンク

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部品番号部品説明メーカ
M-88L70-01P

3V DTMF Receiver

Clare  Inc.
Clare Inc.
M-88L70-01S

3V DTMF Receiver

Clare  Inc.
Clare Inc.
M-88L70-01T

3V DTMF Receiver

Clare  Inc.
Clare Inc.


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