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DAC0830LCN の電気的特性と機能

DAC0830LCNのメーカーはNational Semiconductorです、この部品の機能は「8-Bit P Compatible/ Double-Buffered D to A Converters」です。


製品の詳細 ( Datasheet PDF )

部品番号 DAC0830LCN
部品説明 8-Bit P Compatible/ Double-Buffered D to A Converters
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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DAC0830LCN Datasheet, DAC0830LCN PDF,ピン配置, 機能
May 1999
DAC0830/DAC0832
8-Bit µP Compatible, Double-Buffered D to A Converters
General Description
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, Z80®, and other popular microprocessors. A deposited
silicon-chromium R-2R resistor ladder network divides the
reference current and provides the circuit with excellent tem-
perature tracking characteristics (0.05% of Full Scale Range
maximum linearity error over temperature). The circuit uses
CMOS current switches and control logic to achieve low
power consumption and low output leakage current errors.
Special circuitry provides TTL logic input voltage level com-
patibility.
Double buffering allows these DACs to output a voltage cor-
responding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number
of DACs.
The DAC0830 series are the 8-bit members of a family of
microprocessor-compatible DACs (MICRO-DAC).
Features
n Double-buffered, single-buffered or flow-through digital
data inputs
n Easy interchange and pin-compatible with 12-bit
DAC1230 series
n Direct interface to all popular microprocessors
n Linearity specified with zero and full scale adjust
only — NOT BEST STRAIGHT LINE FIT.
n Works with ±10V reference-full 4-quadrant multiplication
n Can be used in the voltage switching mode
n Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
n Operates “STAND ALONE” (without µP) if desired
n Available in 20-pin small-outline or molded chip carrier
package
Key Specifications
n Current settling time: 1 µs
n Resolution: 8 bits
n Linearity: 8, 9, or 10 bits (guaranteed over temp.)
n Gain Tempco: 0.0002% FS/˚C
n Low power dissipation: 20 mW
n Single power supply: 5 to 15 VDC
Typical Application
BI-FETand MICRO-DACare trademarks of National Semiconductor Corporation.
Z80® is a registered trademark of Zilog Corporation.
© 1999 National Semiconductor Corporation DS005608
DS005608-1
www.national.com

1 Page





DAC0830LCN pdf, ピン配列
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Digital Input
Voltage at VREF Input
Storage Temperature Range
Package Dissipation
at TA=25˚C (Note 3)
DC Voltage Applied to
IOUT1 or IOUT2 (Note 4)
ESD Susceptability (Note 4)
17 VDC
VCC to GND
±25V
−65˚C to +150˚C
500 mW
−100 mV to VCC
800V
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
Operating Conditions
Temperature Range
Part numbers with “LCN” suffix
Part numbers with “LCWM” suffix
Part numbers with “LCV” suffix
Part numbers with “LCJ” suffix
Part numbers with “LJ” suffix
Voltage at Any Digital Input
260˚C
300˚C
215˚C
220˚C
TMINTATMAX
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
−40˚C to +85˚C
−55˚C to +125˚C
VCC to GND
Electrical Characteristics
VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMINTATMAX. For all other limits
TA=25˚C.
Parameter
Conditions
See
Note
VCC = 4.75 VDC
VCC = 15.75 VDC
Typ
(Note 12)
Tested
Limit
(Note 5)
VCC = 5 VDC ±5%
VCC = 12 VDC ±5%
to 15 VDC ±5%
Design
Limit
(Note 6)
Limit
Units
CONVERTER CHARACTERISTICS
Resolution
88
8 bits
Linearity Error Max
Zero and full scale adjusted
4, 8
DAC0830LJ & LCJ
−10VVREF+10V
0.05 0.05 % FSR
DAC0832LJ & LCJ
0.2 0.2 % FSR
DAC0830LCN, LCWM &
LCV
0.05 0.05 % FSR
DAC0831LCN
0.1 0.1 % FSR
DAC0832LCN, LCWM &
LCV
0.2 0.2 % FSR
Differential Nonlinearity
Zero and full scale adjusted
4, 8
Max
DAC0830LJ & LCJ
−10VVREF+10V
0.1 0.1 % FSR
DAC0832LJ & LCJ
0.4 0.4 % FSR
DAC0830LCN, LCWM &
LCV
0.1 0.1 % FSR
DAC0831LCN
0.2 0.2 % FSR
DAC0832LCN, LCWM &
LCV
0.4 0.4 % FSR
Monotonicity
−10VVREF
+10V
LJ & LCJ
LCN, LCWM & LCV
4
8 8 bits
8 8 bits
Gain Error Max
Gain Error Tempco Max
Using Internal Rfb
−10VVREF+10V
Using internal Rfb
7 ±0.2
0.0002
±1
±1
0.0006
% FS
%
FS/˚C
Power Supply Rejection
All digital inputs latched high
VCC=14.5V to 15.5V
11.5V to 12.5V
0.0002
0.0006
0.0025
%
FSR/V
4.5V to 5.5V
0.013
0.015
Reference
Max
15 20 20 k
Input
Min
15 10 10 k
Output Feedthrough Error
VREF=20 Vp-p, f=100 kHz
All data inputs latched low
3
mVp-p
3 www.national.com


3Pages


DAC0830LCN 電子部品, 半導体
Definition of Package Pinouts
Control Signals (All control signals level actuated)
CS:
ILE:
WR1:
Chip Select (active low). The CS in combination
with ILE will enable WR1.
Input Latch Enable (active high). The ILE in combi-
nation with CS enables WR1.
Write 1. The active low WR1 is used to load the digi-
tal input data bits (DI) into the input latch. The data
in the input latch is latched when WR1 is high. To
update the input latch–CS and WR1 must be low
while ILE is high.
WR2:
Write 2 (active low). This signal, in combination with
XFER, causes the 8-bit data which is available in
the input latch to transfer to the DAC register.
XFER: Transfer control signal (active low). The XFER will
enable WR2.
Other Pin Functions
DI0-DI7:
IOUT1:
Digital Inputs. DI0 is the least significant bit (LSB)
and DI7 is the most significant bit (MSB).
DAC Current Output 1. IOUT1 is a maximum for a
digital code of all 1’s in the DAC register, and is
zero for all 0’s in DAC register.
IOUT2:
DAC Current Output 2. IOUT2 is a constant minus
IOUT1 , or IOUT1 + IOUT2 = constant (I full scale for
a fixed reference voltage).
Rfb: Feedback Resistor. The feedback resistor is pro-
Linearity Error
VREF:
VCC:
GND:
vided on the IC chip for use as the shunt feedback
resistor for the external op amp which is used to
provide an output voltage for the DAC. This on-
chip resistor should always be used (not an exter-
nal resistor) since it matches the resistors which
are used in the on-chip R-2R ladder and tracks
these resistors over temperature.
Reference Voltage Input. This input connects an
external precision voltage source to the internal
R-2R ladder. VREF can be selected over the range
of +10 to −10V. This is also the analog voltage in-
put for a 4-quadrant multiplying DAC application.
Digital Supply Voltage. This is the power supply
pin for the part. VCC can be from +5 to +15VDC.
Operation is optimum for +15VDC
The pin 10 voltage must be at the same ground
potential as IOUT1 and IOUT2 for current switching
applications. Any difference of potential (VOS pin
10) will result in a linearity change of
For example, if VREF = 10V and pin 10 is 9mV offset from
IOUT1 and IOUT2 the linearity change will be 0.03%.
Pin 3 can be offset ±100mV with no linearity change, but the
logic input threshold will shift.
DS005608-23
a) End point test after
zero and fs adj.
DS005608-24
b) Best straight line
DS005608-25
c) Shifting fs adj. to pass
best straight line test
Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC0830
has 28 or 256 steps and therefore has 8-bit resolution.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting for
zero and full-scale. Linearity error is a parameter intrinsic to
the device and cannot be externally adjusted.
National’s linearity “end point test” (a) and the “best straight
line” test (b,c) used by other suppliers are illustrated above.
The “end point test’’ greatly simplifies the adjustment proce-
dure by eliminating the need for multiple iterations of check-
ing the linearity and then adjusting full scale until the linearity
is met. The “end point test’’ guarantees that linearity is met
after a single full scale adjust. (One adjustment vs. multiple
iterations of the adjustment.) The “end point test’’ uses a
standard zero and F.S. adjustment procedure and is a much
more stringent test for DAC linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within ±12LSB of the
final output value. Full-scale settling time requires a zero to
full-scale or full-scale to zero output change.
Full Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC0830 series, full scale is VREF −1LSB.
For VREF = 10V and unipolar operation, VFULL-SCALE =
10,0000V–39mV 9.961V. Full-scale error is adjustable to
zero.
www.national.com
6

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共有リンク

Link :


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