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ADC-B207 の電気的特性と機能

ADC-B207のメーカーはETCです、この部品の機能は「7- BIT 20MHZ CMOS FLASH A/D CONVERTERS」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADC-B207
部品説明 7- BIT 20MHZ CMOS FLASH A/D CONVERTERS
メーカ ETC
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ADC-B207 Datasheet, ADC-B207 PDF,ピン配置, 機能
®®
INN O VAT IO N a n d E X C E L L E N C E
ADC-207
7-Bit, 20MHz, CMOS
Flash A/D Converters
FEATURES
7-bit flash A/D converter
20MHz sampling rate
Low power (250mW)
Single +5V supply
1.2 micron CMOS technology
7-bit latched 3-state output with overflow bit
Surface-mount versions
High-reliability version
No missing codes
GENERAL DESCRIPTION
The ADC-207 is the industry’s first 7-bit flash converter using an
advanced high-speed VLSI 1.2 micron CMOS process. This
process offers some very distinctive advantages over other
processes, making the ADC-207 unique. The smaller
geometrics of the process achieve high speed, better linearity
and superior temperature performance.
Since the ADC-207 is a CMOS device, it also has very low
power consumption (250mW). The device draws power from
a single +5V supply and is conservatively rated for 20MHz
operation. The ADC-207 allows using sampling apertures as
small as 12ns, making it more closely approach an ideal
sampler. The small sampling apertures also let the device
operate at greater than 20MHz.
The ADC-207 has 128 comparators which are auto-balanced
on every conversion to cancel out any offsets due to
temperature and/or dynamic effects. The resistor ladder has a
midpoint tap for use with an external voltage source to improve
integral linearity beyond 7 bits. The ADC-207 also provides the
user with 3-state outputs for easy interfacing to other
components.
There are six models of the ADC-207 covering two operating
temperature ranges, 0 to +70°C and –55 to +125°C. Two high-
reliability "QL" models are also available.
ANALOG INPUT 4
+REFERENCE 6
R/2
+VDD
+5V SUPPLY 18
R
DIGITAL GROUND 2
ANALOG GROUND 7
R
RANGE MIDPOINT 5
R/2
R/2
2
1
R
–REFERENCE 3
R
CS1 8
CS2 9
D
GQ
D
GQ
128-TO-7
ENCODER
D
GQ
D
GQ
D
GQ
2
1
CLOCK
GENERATOR
1 CLOCK INPUT
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
10 OVERFLOW
11 BIT 1 (MSB)
12 BIT 2
13 BIT 3
14 BIT 4
15 BIT 5
16 BIT 6
17 BIT 7 (LSB)
INPUT/OUTPUT
CONNECTIONS
DIP
PINS
FUNCTION
LCC
PINS
1 CLOCK INPUT
2 DIGITAL GROUND
3 –REFERENCE
4 ANALOG INPUT
5 MIDPOINT
6 +REFERENCE
7 ANALOG GROUND
8 CS1
9 CS2
10 OVERFLOW
11 BIT 1 (MSB)
12 BIT 2
13 BIT 3
14 BIT 4
15 BIT 5
16 BIT 6
17 BIT 7 (LSB)
18 +5V SUPPLY
1
4
5
6
7
8
9
11
12
13
14
16
17
19
20
21
23
24
Figure 1. ADC-207 Functional Block Diagram (DIP Pinout)
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.) Tel: (508) 339-3000 Fax: (508) 339-6356 For immediate assistance (800) 233-2765

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ADC-B207 pdf, ピン配列
®®
ADC-207
OUTPUT CODING
(+REFERENCE = +5.12V, –REFERENCE = ground, MIDPOINT = no connection)
NOTE:
The reference should be held to ±0.1% accuracy or
better. Do not use the +5V power supply as a
reference input without precision regulation and high
frequency decoupling.
Values shown here are for a +5.12V reference. Scale other
references proportionally. Calibration equipment should test for
code changes at the midpoints between these center values
shown in Table 1. For example, at the half-scale major carry,
set the input to 2.54V and adjust the reference until the code
flickers equally between 63 and 64. Note also that the
weighting for the comparator resistor network leaves the first
and last thresholds within 1/2LSB of the end points to adjust
the code transition to the proper midpoint values.
CLOCK
OUTPUT
DATA
TIMING DIAGRAM
1
AUTO
ZERO
2
SAMPLE
N
1
AUTO
ZERO
2
SAMPLE
N+1
1
AUTO
ZERO
2
SAMPLE
N+2
25ns max.
N DATA
N+1 DATA
25ns max.
Table 1. ADC-207 Output Coding
Analog Input
(Center Value)
0.00V
+0.04V
+1.28V
+2.52V
+2.56V
+2.60V
+3.84V
+5.08V
+5.12V
Code
Zero
+1LSB
+1/4FS
+1/2FS – 1LSB
+1/2FS
+1/2FS + 1LSB
+3/4FS
+FS
Overflow
Overflow
0
0
0
0
0
0
0
0
1
1234567
MSB
LSB
0000000
0000001
0100000
0111111
1000000
1000001
1100000
1111111
1111111
*Note that the overflow code does not clear the data bits.
Decimal
0
1
32
63
64
65
96
127
255*
Hexadecimal
(Incl. 0V)
00
01
20
3F
40
41
60
7F
FF
ADC-207 OPERATION
The ADC-207 uses a switched capacitor scheme in which
there is an auto-zero phase and a sampling phase. See
Figure 1 and Timing Diagram. The ADC-207 uses a single
clock input. When the clock is at a high state (logic 1), the
ADC-207 is in the auto-zero phase (Ø1). When the clock is at
a low state (logic 0), the ADC-207 is in the sampling phase
(Ø2). During phase 1, the 128 comparator outputs are shorted
to their inputs through CMOS switches. This serves the
purpose of bringing the inputs and outputs to the transition
levels of the respective comparators. The inputs to the
comparators are also connected to 128 sampling capacitors.
The other end of the 128 capacitors are also shorted to 128
taps of a resistor ladder, via CMOS switches. Therefore, during
phase 1 the sampling capacitors are charged to the differential
voltage between a resistor tap and its respective comparator
transition voltage.
This eliminates offset differences between comparators and
yields better temperature performance. During phase 2 (Ø2) the
input voltage is applied to the 128 capacitors, via CMOS
switches. This forces the comparators to trip either high or low.
Since the comparators during phase 1 were sitting at their
transition point, they can trip very quickly to the correct state.
Also during phase 2, the outputs of the comparators are loaded
into internal latches which in turn feed a128-to-7 encoder. When
going back into phase 1, the output of the encoder is loaded into
an output latch. This latch then feeds the 3-state output buffer.
This means that the ADC-207 is of pipeline design. To do a
single conversion, the ADC-207 requires a positive pulse
followed by a negative pulse followed by a positive pulse.
Continuous conversion requires one cycle/sample (one positive
pulse and one negative pulse). The 3-state buffer has two
enable lines, CS1 and CS2. Table 2 shows the truth table for
chip select signals. CS1 has the function of enabling/disabling
bits 1 through 7. CS2 has the function of enabling/disabling
bits 1 through 7 and the overflow bit. Also, a full-scale input
produces all ones, including the overflow bit at the output. The
ADC-207 has an adjustable resistor ladder string. The top end,
idle point, and bottom end are brought out for use with
applications circuits.
These pins are called +REFERENCE, MIDPOINT and
–REFERENCE, respectively. In typical operation
+REFERENCE is tied to +5V, –REFERENCE is tied to ground,
and MIDPOINT is bypassed to ground. Such a configuration
results in a 0 to +5V input voltage range. The MIDPOINT pin
can also be tied to a +2.5V source to further improve integral
linearity. This is usually not necessary unless better than 7-bit
linearity is needed.
Table 2. Chip Select Truth Table
CS1 CS2
Bits 1-7
Overflow Bit
00
10
01
11
3-State Mode
3-State Mode
Data Outputed
3-State Mode
3-State Mode
3-State Mode
Data Outputed
Data Outputed
NOTE: Reduce the sample time (sample pulse)
3


3Pages


ADC-B207 電子部品, 半導体
ADC-207
®®
MECHANICAL DIMENSIONS INCHES (MM)
18-Pin Ceramic DIP
18
1
0.200 MAX.
(5.1 MAX.)
0.960 MAX.
(24.38 MAX.)
DATEL
ADC-207MC
PIN 1
IDENTIFIER
10
0.220/0.310
(5.59 / 7.87)
9
0.015/0.060
(0.38/1.52)
0.014/0.023 0.100 TYP.
(0.35/0.58) (2.540)
SEATING
PLANE
0.035
(0.889)
0.008/0.015
(0.20/0.38)
0.290/0.320
(7.36/8.13)
24-Pin Ceramic LCC
+0.010
0.400 –0.005
+0.25
(10.16 –0.13 )
16
24
1
4
+0.010
0.400 –0.005
+0.25
(10.16 –0.13 )
10
TOP VIEW
0.090 MAX.
(2.29 MAX.)
0.020 ±0.005
(0.51 ±0.13)
0.050
(1.270)
TYP.
PIN 1
INDEX
0.250 ±0.005
(6.35 ±0.13)
0.250 ±0.005
(6.35 ±0.13)
ORDERING INFORMATION
MODEL
ADC-207MC
ADC-207MM
ADC-207MM-QL
ADC-207LC
ADC-207LM
ADC-207LM-QL
ACCESSORIES
ADC-B207/208
TEMP. RANGE
0 to +70°C
–55 to +125°C
–55 to +125°C
0 to +70°C
–55 to +125°C
–55 to +125°C
PACKAGE
18-pin DIP
18-pin DIP
18-pin DIP
24-pin CLCC
24-pin CLCC
24-pin CLCC
Evaluation Board for DIP Version
(without ADC-207)
®®
IN N O VAT IO N a n d E X C E L L E N C E
ISO 9001
REGISTERED
DS-0038C 12/04
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
Internet: www.datel.com E-mail:[email protected]
Data Sheet Fax Back: (508) 261-2857
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444
DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01
DATEL GmbH München, Germany Tel: 89-544334-0
DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025
DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein
do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.

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共有リンク

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部品番号部品説明メーカ
ADC-B207

7- BIT 20MHZ CMOS FLASH A/D CONVERTERS

ETC
ETC
ADC-B208

7- BIT 20MHZ CMOS FLASH A/D CONVERTERS

ETC
ETC


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