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PDF AD775 Data sheet ( Hoja de datos )
| Número de pieza | AD775 | |
| Descripción | 8-Bit 20 MSPS/ 60 mW Sampling A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD775 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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a
8-Bit 20 MSPS, 60 mW
Sampling A/D Converter
AD775
FEATURES
CMOS 8-Bit 20 MSPS Sampling A/D Converter
Low Power Dissipation: 60 mW
+5 V Single Supply Operation
Differential Nonlinearity: 0.3 LSB
Differential Gain: 1%
Differential Phase: 0.5 Degrees
Three-State Outputs
On-Chip Reference Bias Resistors
Adjustable Reference Input
Video Industry Standard Pinout
Small Packages:
24-Pin 300 Mil SOIC Surface Mount
24-Pin 400 Mil Plastic DIP
PRODUCT DESCRIPTION
The AD775 is a CMOS, low power, 8-bit, 20 MSPS sampling
analog-to-digital converter (ADC). The AD775 features a built-
in sampling function and on-chip reference bias resistors to pro-
vide a complete 8-bit ADC solution. The AD775 utilizes a
pipelined/ping pong two-step flash architecture to provide high
sampling rates (up to 35 MHz) while maintaining very low
power consumption (60 mW).
Its combination of excellent DNL, fast sampling rate, low dif-
ferential gain and phase errors, extremely low power dissipation,
and single +5 V supply operation make it ideally suited for a
variety of video and image acquisition applications, including
portable equipment. The AD775’s reference ladder may be con-
nected in a variety of configurations to accommodate different
input ranges. The low input capacitance (11 pF typical) provides
an easy-to-drive input load compared to conventional flash
converters.
The AD775 is offered in both 300 mil SOIC and 400 mil DIP
plastic packages, and is designed to operate over an extended
commercial temperature range (–20°C to +75°C).
FUNCTIONAL BLOCK DIAGRAM
AVDD
18 14 15
AVDD
VIN
19
AD775
DVDD
13 11
VRTS 16
VRT 17
15 COARSE
COMPARATORS
FINE COMPARATORS
BANK A
VRB 23
VRBS 22
255
AVSS
20 21
AVSS
FINE COMPARATORS
BANK B
CLOCK LOGIC
12
CLK
4
8
5
2 24
DVSS
10 D7 (MSB)
9
8
7
6
5
4
3 D0 (LSB)
1 OE
PRODUCT HIGHLIGHTS
Low Power: The AD775 has a typical supply current of 12 mA,
for a power consumption of 60 mW. Reference ladder current
is also low: 6.6 mA typical, minimizing the reference power
consumption.
Complete Solution: The AD775’s switched capacitor design
features an inherent sample/hold function: no external SHA is
required. On-chip reference bias resistors are included to allow
a supply-based reference to be generated without any external
resistors.
Excellent Differential Nonlinearity: The AD775 features a
typical DNL of 0.3 LSBs, with a maximum limit of 0.5 LSBs.
No missing codes is guaranteed.
Single +5 V Supply Operation: The AD775 is designed to oper-
ate on a single +5 V supply, and the reference ladder may be
configured to accommodate analog inputs inclusive of ground.
Low Input Capacitance: The 11 pF input capacitance of the
AD775 can significantly decrease the cost and complexity of
input driving circuitry, compared with conventional 8-bit flash
ADCs.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD775
54
48
42
36
30
24
18
12
6
0
0.1 1 10
fIN – MHz
Figure 2. S/(N + D) vs. Input Frequency at 20 MSPS Clock
Rate (VIN = –0.3 dB)
–30
–36
–42
–48
–54
0.1
1
fIN – MHz
10
Figure 5. THD vs. Input Frequency at 20 MSPS Clock Rate
(VIN = –0.3 dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
FREQUENCY – MHz
Figure 3. Typical FFT at 1 MHz Input, 20 MSPS Clock Rate
(VIN = –0.5 dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
FREQUENCY – MHz
Figure 6. Typical FFT at 5 MHz Input, 20 MSPS Clock Rate
(VIN = –0.5 dB)
+0.4
+0.3
+0.2
+0.1
0
–0.1
–0.2
–0.3
–0.4
–FULLSCALE
+FULLSCALE
Figure 4. Typical Differential Nonlinearity (DNL)
+1
0
–1
–FULLSCALE
+FULLSCALE
Figure 7. Typical Integral Nonlinearity (INL)
REV. 0
–5–
5 Page 
AD775
Figure 18. Silkscreen Layer (Not to Scale)
Figure 20. Solder Side PCB Layout (Not to Scale)
Figure 19. Component Side PCB Layout (Not to Scale)
Figure 21. Ground Plane PCB Layout (Not to Scale)
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD775.PDF ] | |
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