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ADV7175A の電気的特性と機能

ADV7175AのメーカーはAnalog Devicesです、この部品の機能は「Digital CCIR-601 to PAL/NTSC Video Encoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADV7175A
部品説明 Digital CCIR-601 to PAL/NTSC Video Encoder
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADV7175A Datasheet, ADV7175A PDF,ピン配置, 機能
a
High Quality, 10-Bit, Digital CCIR-601
to PAL/NTSC Video Encoder
ADV7175A/ADV7176A*
FEATURES
CCIR and Square Pixel Operation
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder
High Quality 10-Bit Video DACs
Integral Nonlinearity <1 LSB at 10 Bits
Integrated Subcarrier Locking to External Video Source
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
NTSC-M, PAL-M/N, PAL-B/D/G/H/I
Single 27 MHz Clock Required (؋2 Oversampling)
80 dB Video SNR
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision Antitaping Rev 7.01 (ADV7175A Only)**
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
Onboard Color Bar Generation
Component S-Video (Y/C)
Component YUV and RGB
EuroSCART Output (RGB + CVBS/LUMA)
Onboard Voltage Reference
2-Wire Serial MPU Interface (I2C Compatible)
Single Supply 5 V or 3 V Operation
Video Input Data Port Supports:
Small 44-Lead MQFP Thermally Enhanced Package
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
Full Video Output Drive or Low Signal Drive Capability
34.7 mA max into 37.5 (Doubly-Terminated 75R)
5 mA min with External Buffers
APPLICATIONS
MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/
Cable Systems (Set Top Boxes/IRDs), Digital TVs,
CD Video/Karaoke, Video Games, PC Video/Multimedia
Programmable Simultaneous Composite
and S-Video Y/C or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass/Notch/Extended)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Individual ON/OFF Control of Each DAC
GENERAL DESCRIPTION
The ADV7175A/ADV7176A is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 8 or 16-bit component
video data into a standard analog baseband television signal
(Continued on page 11)
FUNCTIONAL BLOCK DIAGRAM
TTX
TTXREQ
VAA
COLOR
DATA
P7–P0
P15–P8
HSYNC
FIELD/VSYNC
BLANK
TELETEXT
INSERTION
BLOCK
8
4:2:2 TO 8
4:4:4
INTER-
POLATOR
8
YCrCb
TO
YUV
MATRIX
VIDEO TIMING
GENERATOR
8
8
ADD
INTER-
8
Y
LOW-PASS
SYNC
POLATOR
FILTER
YUV TO
RBG
MATRIX
10
M
U
L
10
T
I
P 10
L
E
X 10
E
R
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
8
ADD 8
INTER-
8
U 10
LOW-PASS
BURST
POLATOR
FILTER
8 ADD 8
BURST
INTER- 8
POLATOR
V 10
LOW-PASS
FILTER
10 10-BIT
DAC
ADV7175A/ADV7176A
I2C MPU PORT
REAL-TIME
CONTROL
CIRCUIT
10 10
SIN/COS
DDS BLOCK
VOLTAGE
REFERENCE
CIRCUIT
DAC D (PIN 27)
DAC C (PIN 26)
DAC B (PIN 31)
DAC A (PIN 32)
VREF
RSET
COMP
CLOCK RESET SCLOCK SDATA ALSB
SCRESET/RTC
GND
The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

1 Page





ADV7175A pdf, ピン配列
ADV7175A/ADV7176A
3.3 V SPECIFICATIONS (VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 . All specifications TMIN to TMAX2 unless otherwise noted)
Parameter
Conditions1
Min Typ Max Unit
STATIC PERFORMANCE3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
10 Bits
± 1 LSB
± 1 LSB
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN3, 4
Input Current, IIN3, 5
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current3
Three-State Output Capacitance3
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
ISOURCE = 400 µA
ISINK = 3.2 mA
2V
0.8 V
± 1 µA
± 50 µA
10 pF
2.4
0.4
10
10
V
V
µA
pF
ANALOG OUTPUTS3
Output Current6, 7
Output Current8
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
POWER REQUIREMENTS3, 9
VAA
Normal Power Mode
IDAC (max)10
IDAC (min)10
ICCT9
Low Power Mode
IDAC (max)10
IDAC (min)10
ICCT11
Power Supply Rejection Ratio
IOUT = 0 mA
COMP = 0.1 µF
16.5
17.35 18.5
mA
5 mA
2.0 %
0 1.4 V
15 k
30 pF
3.0
3.3 3.6
V
150 155
20
45
mA
mA
mA
75
15
45
0.01 0.5
mA
mA
mA
%/%
NOTES
11The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
12Temperature range TMIN to TMAX: 0°C to 70°C.
13 Guaranteed by characterization.
14All digital input pins except pins RESET and RTC/SCRESET.
15Excluding all digital input pins except pins RESET and RTC/SCRESET.
16Full drive into 37.5 load.
17DACs can output 35 mA typically at 3.3 V (RSET = 150 and RL = 75 ), optimum performance obtained at 18 mA DAC current (RSET = 300 and RL = 150 .
18Minimum drive current (used with buffered/scaled output load).
19Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C.
10IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces IDAC correspondingly.
11ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
REV. C
–3–


3Pages


ADV7175A 電子部品, 半導体
ADV7175A/ADV7176A
5 V TIMING SPECIFICATIONS (VAA = 4.75 V–5.25 V1, VREF = 1.235 V, RSET = 150 . All specifications TMIN to TMAX2 unless
otherwise noted.)
Parameter
MPU PORT3, 4
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
Conditions
Min Typ Max Unit
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
0
4.0
4.7
4.0
4.7
250
4.7
100 kHz
µs
µs
µs
µs
ns
1 µs
300 ns
µs
5 ns
0 ns
CLOCK CONTROL
AND PIXEL PORT3, 6
FCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
TELETEXT PORT3, 7
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3, 4
RESET Low Time
27 MHz
8 ns
8 ns
3.5 ns
4 ns
4 ns
3 ns
24 ns
4 ns
37 Clock Cycles
20 ns
1 ns
2 ns
6 ns
NOTES
1The max/min specifications are guaranteed over this range.
2Temperature range TMIN to TMAX: 0°C to 70°C.
3TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
P15P0
HSYNC, FIELD/VSYNC, BLANK
Clock Input:
CLOCK
7Teletext Port consists of the following:
Teletext Output:
TTXREQ
Teletext Input:
TTX
Specifications subject to change without notice.
–6– REV. C

6 Page



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部品番号部品説明メーカ
ADV7175

Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder

Analog Devices
Analog Devices
ADV7175A

Digital CCIR-601 to PAL/NTSC Video Encoder

Analog Devices
Analog Devices


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