DataSheet.jp

ADV473 の電気的特性と機能

ADV473のメーカーはAnalog Devicesです、この部品の機能は「CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADV473
部品説明 CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




このページの下部にプレビューとADV473ダウンロード(pdfファイル)リンクがあります。

Total 12 pages

No Preview Available !

ADV473 Datasheet, ADV473 PDF,ピン配置, 機能
a
CMOS 135 MHz True-Color Graphics
Triple 8-Bit Video RAM-DAC
ADV473
FEATURES
ADV478/ADV471 (ADV®) Register Level Compatible
IBM PS/2,* VGA*/XGA* Compatible
135 MHz Pipelined Operation
Triple 8-Bit D/A Converters
Triple 256 ؋ 8 (256 ؋ 24) Color Palette RAM
Three 15 ؋ 8 Overlay Registers
On-Board Voltage Reference
RS-343A/RS-170 Compatible Analog Outputs
TTL Compatible Digital Inputs and Outputs
Sync on All Three Channels
Programmable Pedestal (0 or 7.5 IRE)
Standard MPU l/O Interface
+5 V CMOS Monolithic Construction
68-Pin PLCC Package
APPLICATIONS
High Resolution Color Graphics
True-Color Visualization
CAE/CAD/CAM
Image Processing
Desktop Publishing
MODES
24-Bit True Color
8-Bit Pseudo Color
15-Bit True Color
8-Bit True Color
SPEED GRADES
135 MHz, 110 MHz
80 MHz, 66 MHz
GENERAL DESCRIPTION
The ADV473 is a complete analog output, Video RAM-DAC
on a single CMOS monolithic chip. The part is specifically
designed for true-color computer graphics systems.
The ADV473 integrates a number of graphic functions onto one
device allowing 24-bit direct true-color operation at the maxi-
mum screen update rate of 135 MHz. It can also be used in
other modes, including 15-bit true color and 8-bit pseudo or in-
dexed color. The ADV473 is fully PS/2 and VGA register level
compatible. It is also capable of implementing IBM’s XGA
standard.
(Continued on page 4)
FUNCTIONAL BLOCK DIAGRAM
VREFIN
VREFOUT
SYNC
BLANK
S0
S1
OL0
OVERLAYS
OL3
R0
RED
R7
G0
GREEN
G7
B0
BLUE
B7
P
I
4X
E
L
P
8 O8
R
T
88
88
SWITCHING
MATRIX &
PIXEL
MASK
8
8
8
OVERLAY PALETTE
15 x 8 RAM
15 x 8 RAM
15 x 8 RAM
8 88
RED
256 x 8
RAM
COLOR
PALETTE
GREEN
256 x 8
RAM
BLUE
256 x 8
RAM
8
8
8
8
8
8
COLOR
PALETTE/
OVERLAY
PALETTE
SWITCHER
8
8
8
D
A
C
P
O
R
T
VOLTAGE
REFERENCE
GENERATOR
VOLTAGE
REFERENCE
CONTROL
CIRCUIT
8 RED
DAC
8 GREEN
DAC
8 BLUE
DAC
OPA
IOR
IOG
IOB
CLOCK
MODE CONTROL PIXEL MASK
REGISTERS
REGISTERS
8
RED
REG
8
GREEN
REG
8
BLUE
REG
MPU PORT
8
ADDRESS
REG
MPU & PIXEL
PORT
CONTROL LOGIC
ADV473
CR0
CR1
CR2
CR3
D0–D7
RD WR RS0 RS1 RS2
ADV is a registered trademark of Analog Devices Inc.
*Personal System/2 and VGA are trademarks of International Business Machines Corp.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703

1 Page





ADV473 pdf, ピン配列
ADV473
TIMING CHARACTERISTICS1
(VAA2 = 5 V; VREF = 1.235 V; RL = 37.5 , CL = 10 pF; RSET = 140 .
All specifications TMIN to TMAX3 unless otherwise noted.)
Parameter
135 MHz
Version
110 MHz
Version
80 MHz
Version
66 MHz
Version
Units
Conditions/Comments
fmax
t1
t2
t34
t44
t55
t65
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t196
tSK
tPD
135
10
10
3
40
20
5
10
10
100
50
40
2
2
7.4
3
2
30
3
13
2
4 × t14
110
10
10
3
40
20
5
10
10
100
50
40
3
3
9.1
3.5
3
30
3
13
2
4 × t14
80
10
10
3
40
20
5
10
10
100
50
40
3
3
12.5
4
4
30
3
13
2
4 × t14
66
10
10
3
40
20
5
10
10
100
50
40
3
3
15.15
5
5
30
3
13
2
4 × t14
MHz
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
ns max
ns max
ns
Clock Rate
RS0–RS2 Setup Time
RS0–RS2 Hold Time
RD Asserted to Data Bus Driven
RD Asserted to Data Valid
RD Negated to Data Bus 3-Stated
Read Data Hold Time
Write Data Setup Time
Write Data Hold Time
CR0–CR3 Delay Time
RD, WR Pulse Width Low
RD, WR Pulse Width High
Pixel & Control Setup Time
Pixel & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Settling Time
Analog Output Skew
Pipeline Delay
NOTES
1TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load 10 pF, D0-D7 output load 50 pF. See timing notes in Figure 2.
2VAA = 5 V ± 5%.
3Temperature range (TMIN to TMAX); 0°C to +70°C; TJ (Silicon Junction Temperature) 100°C .
4t3 and t4 are measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.4 V or 2.4 V.
5t5 and t6 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 3. The measured number is
then extrapolated back to remove the effects of charging the 50 pF capacitor. This means that the times, t 5 and t6, quoted in the timing characteristics are the
true values for the device and, as such, are independent of external bus loading capacitances.
6Settling time does not include clock and data feedthrough.
Specifications subject to change without notice.
RS0, RS1,
RS2
RD, WR
D0–D7
(READ)
D0–D7
(WRITE)
t1
VALID
t2
t4
t3
CR0–CR3
t10
t5
DATA OUT (RD = 0)
t6
DATA IN (WR = 0)
t7 t8
t11
t9
Figure 1. MPU Read/Write Timing
t14
t15 t16
CLOCK
R0-R7, G0–G7,
B0–B7,
DATA
OL0-OL3, S0–S1,
SYNC, BLANK
IOR, IOG, IOB
t12 t17 t19
t13
NOTES
t18
1. OUTPUT DELAY MEASURED FROM THE 50% POINT OF THE RISING EDGE
OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. SETTLING TIME MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO THE OUTPUT REMAINING WITHIN ±1 LSB.
3. OUTPUT RISE/FALL TIME MEASURED BETWEEN THE 10% AND 90%
POINTS OF FULL-SCALE TRANSITION.
TO
OUTPUT
PIN
50pF
3.2mA
+2.1V
400µA
Figure 2. Video Input/Output Timing
Figure 3. Load Circuit for Bus
Access and Relinquish Time
REV. A
–3–


3Pages


ADV473 電子部品, 半導体
ADV473
TERMINOLOGY
BLANKING LEVEL
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
COLOR VIDEO (RGB)
This usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
COMPOSITE SYNC SIGNAL (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
COMPOSITE VIDEO SIGNAL
The video signal with or without setup, plus the composite
SYNC signal.
GRAY SCALE
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different lev-
els while a 6-bit DAC contains 64.
RASTER SCAN
The most basic method of sweeping a CRT one line at a time to
generate and to display images.
REFERENCE BLACK LEVEL
The maximum negative polarity amplitude of the video signal.
REFERENCE WHITE LEVEL
The maximum positive polarity amplitude of the video signal.
SETUP
The difference between the reference black level and the blank-
ing level.
SYNC LEVEL
The peak level of the composite SYNC signal.
VIDEO SIGNAL
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
CIRCUIT DESCRIPTION
MPU Interface
The ADV473 supports a standard MPU bus interface, allowing
the MPU direct access to the color palette RAM and overlay
color registers.
Three address decode lines, RS0–RS2, specify whether the
MPU is accessing the address register, the color palette RAM,
the overlay registers, or read mask register. These controls also
determine whether this access is a read or write function. Table
I illustrates this decoding. The 8-bit address register is used to
address the contents of the color palette RAM and overlay
registers.
Table I. Control Input Truth Table
RS2 RS1 RS0 Addressed by MPU
0 0 0 Address Register (RAM Write Mode)
0 1 1 Address Register (RAM Read Mode)
0 0 1 Color Palette RAM
0 1 0 Pixel Read Mask Register
1 0 0 Address Register (Overlay Write Mode)
1 1 1 Address Register (Overlay Read Mode)
1 0 1 Overlay Registers
1 1 0 Command Register
Color Palette Writes
The MPU writes to the address register (selecting RAM write
mode, RS2 = 0, RS1 = 0 and RS0 = 0) with the address of the
color palette RAM location to be modified. The MPU performs
three successive write cycles (8 or 6 bits each of red, green, and
blue), using RS0–RS2 to select the color palette RAM (RS2 =
0, RS1 = 0, RS0 = 1). After the BLUE write cycle, the three
bytes of color information are concatenated into a 24-bit word
or an 18-bit word and written to the location specified by the
address register. The address register then increments to the
next location which the MPU may modify by simply writing an-
other sequence of red, green, and blue data. A complete set of
colors can be loaded into the palette by initially writing the start
address and then performing a sequence of RED, GREEN and
BLUE writes. The address automatically increments to the next
highest location after a BLUE write.
Color Palette Reads
The MPU writes to the address register (selecting RAM read
mode, RS2 = 0, RS1 = 1 and RS0 = 1) with the address of the
color palette RAM location to be read back. The contents of the
palette RAM are copied to the RED, GREEN and BLUE regis-
ters and the address register increments to point to the next pal-
ette RAM location. The MPU then performs three successive
read cycles (8 or 6 bits each of red, green, and blue), using
RS0–RS2 to select the color palette RAM (RS2 = 0, RS1 = 0,
RS0 = 1). After the BLUE read cycle, the 24/18 bit contents of
the palette RAM at the location specified by the address register
is loaded into the RED, GREEN and BLUE registers. The ad-
dress register then increments to the next location which the
MPU can read back by simply reading another sequence of red,
green, and blue data. A complete set of colors can be read back
from the palette by initially writing the start address and then
performing a sequence of RED, GREEN and BLUE reads. The
address automatically increments to the next highest location
after a BLUE read.
–6– REV. A

6 Page



ページ 合計 : 12 ページ
 
PDF
ダウンロード
[ ADV473 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
ADV471

CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs

Analog Devices
Analog Devices
ADV473

CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC

Analog Devices
Analog Devices
ADV475

Power-Down Color Palette RAM-DAC

Analog Devices
Analog Devices
ADV476

CMOS Monolithic 256x18 Color Palette RAM-DAC

Analog Devices
Analog Devices


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap