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ADV7202 の電気的特性と機能

ADV7202のメーカーはAnalog Devicesです、この部品の機能は「Simultaneous Sampling Video Rate Codec」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADV7202
部品説明 Simultaneous Sampling Video Rate Codec
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADV7202 Datasheet, ADV7202 PDF,ピン配置, 機能
PRELIMINARY TECHNICAL DATA
a
Simultaneous Sampling
Video Rate Codec
Preliminary Technical Data
ADV7202
FEATURES
Four 10-Bit Video DACs (4:2:2, YCrCb, RGB I/P
Supported)
10-Bit Video Rate Digitization at Up to 54 Mhz
AGC Control (؎6 dB)
Front-End 3-Channel Clamp Control
Up to Five CVBS Input Channels, Two Component YUV,
Three S-Video, or a combination of the above. Simul-
taneous Digitization of Two CVBS Input Channels.
Aux 8-Bit SAR ADC @ 843 kHz Sampling Giving up to
Eight General Purpose Inputs
I2C and SPI Compatible Interface with I2C Filter
RGB Inputs for Picture-on-Picture of the RGB DACs
APPLICATIONS
Picture-on-Picture Video Systems
Simultaneous Video Rate Processing
Hybrid Set-Top Box TV Systems
Direct Digital Synthesis/I-Q Demodulation
Image Processing
GENERAL DESCRIPTION
The ADV7202 is a video rate sampling Codec.
It has the capability of sampling up to five NTSC/PAL/SECAM
video I/P signals. The resolution on the front-end digitizer is
12 bits; 2 bits (12 dB) are used for gain and offset adjustment.
The digitizer has a conversion rate of 54 MHz.
It also has up to eight auxiliary inputs that can be sampled by
an 843 kHz SAR ADC for system monitoring, etc.
The back end consists of four 10-bit DACs that run at up to
54 MHz and can be used to output CVBS, S-Video, Component
YCrCb, and RGB.
This Codec also supports Picture-on-Picture with the 3-channel
I/P mux that also muxes to the DAC O/Ps.
The ADV7202 can operate at 3.3 V or 5 V. Its monolithic CMOS
construction ensures greater functionality with lower power
dissipation.
The ADV7202 is packaged in a small 64-lead LQFP package.
FUNCTIONAL BLOCK DIAGRAM
DOUT DAC DATA
XTAL [9:0]
[9:0]
OSD I/P "S"
AIN1P
AIN1M
AIN2P
AIN2M
AIN3P
AIN3M
AIN4P
AIN4M
AIN5P
AIN5M
AIN6P
AIN6M
I/P
MUX
SHA AND
CLAMP
SHA AND
CLAMP
SHA AND
CLAMP
MUX
ADC BLOCK
12-BIT
A/D
A/D
8-BIT 843KHz
ADV7202
ADC
DAC
LOGIC LOGIC
10-BIT
D/A
10-BIT
D/A
10-BIT
D/A
10-BIT
D/A
12C/SPI
DAC0
DAC1
DAC2
DAC3
REV. PrB
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

1 Page





ADV7202 pdf, ピン配列
PRELIMINARY TECHNICAL DATA
ADV7202
5 V SPECIFICATIONS (AVDD/DVDD = 5 V ؎ 5%, VREF = 1.235 V RSET = 1.2 k, all specifications TMIN to TMAX unless otherwise noted.)
Parameter
Min Typ Max
Unit
Test Conditions
POWER REQUIREMENTS1
AVDD/DVDD
Normal Power Mode
IDAC2
IDSC3
IADC4
Sleep Mode
Current
PSU Rejection Ratio
DACs
Video ADC
Aux ADC
Power-Up Time
MPU PORT—I2C5
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
MPU PORT—SPI5, 6
SCLOCK Frequency
SCLOCK High Pulsewidth, t21
SCLOCK Low Pulsewidth, t22
SI Data Setup Time, t20
SI Data Hold Time, t19
RESET Low Time
4.75
0
0.6
1.3
0.6
0.6
100
0.6
0
TBD
TBD
TBD
TBD
100
5
4
34
21
100
0.01
0.01
TBD
TBD
5.25
0.5
0.5
TBD
400
300
300
10
TBD
TBD
TBD
TBD
V
mA
mA
mA
µA
%/%
%/%
TBD
TBD
kHz
µs
µs
µs
µs
ns
ns
ns
µs
MHz
kHz
ns
ns
ns
ns
RSET = 1.2 k, RL = 300
RSET = 1.2 k, RL = 300
COMP = 0.1 µF
TBD
Ref. power-up time
After this period the first clock is
generated.
Relevant for Repeated Start Condition
NOTES
1All DACs and ADCs on.
2IDAC is the DAC supply current.
3IDSC is the digital core supply current.
4IADC is the ADC supply current.
5TTL input values are 0 V to 3 V, with input rise/fall times 3 ns, as measured between the 10% and 90% points.
Timing reference points at 50% for inputs and outputs.
6See SPI timing diagram Figures 10 and 11.
Specifications subject to change without notice.
REV. PrB
–3–


3Pages


ADV7202 電子部品, 半導体
PRELIMINARY TECHNICAL DATA
ADV7202–SPECIFICATIONS
3.3 V SPECIFICATIONS (AVDD/DVDD = 3.3 V ؎ 5%, VREF = 1.235 V RSET = 1.2 k, all specifications TMIN to TMAX unless otherwise noted.)
Parameter
Min Typ Max
Unit
Test Conditions
POWER REQUIREMENTS1
AVDD/DVDD
Normal Power Mode
IDAC2
IDSC3
IADC4
Sleep Mode
Current
PSU Rejection Ratio
DACs
Video ADC
Aux ADC
Power-Up Time
3.15 3.3 3.45
V
4 mA
34 mA
21 mA
100 µA
0.01
0.01
TBD
TBD
0.5
0.5
TBD
%/%
%/%
TBD
TBD
RSET = 1.2 k, RL = 300
RSET = 1.2 k, RL = 300
COMP = 0.1 µF
TBD
TBD
MPU PORT—I2C5
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
MPU PORT—SPI5, 6
SCLOCK Frequency
SCLOCK High Pulsewidth, t21
SCLOCK Low Pulsewidth, t22
SI Data Setup Time, t20
SI Data Hold Time, t19
RESET Low Time
0
0.6
1.3
0.6
0.6
100
0.6
TBD
TBD
TBD
TBD
TBD
100
400
300
300
TBD
TBD
TBD
TBD
TBD
kHz
µs
µs
µs
µs
ns
ns
ns
µs
kHz
kHz
ns
ns
ns
ns
After this period the first clock is
generated.
Relevant for Repeated Start Condition
NOTES
1All DACs and ADCs on.
2IDAC is the DAC supply current.
3IDSC is the digital core supply current.
4IADC is the ADC supply current.
5TTL input values are 0 V to 3 V, with input rise/fall times 3 ns, as measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
6See SPI timing diagram Figures 10 and 11.
Specifications subject to change without notice.
–6– REV. PrB

6 Page



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部品番号部品説明メーカ
ADV7202

Simultaneous Sampling Video Rate Codec

Analog Devices
Analog Devices


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