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PDF ISL12022 Data sheet ( Hoja de datos )
| Número de pieza | ISL12022 | |
| Descripción | Low Power RTC | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Low Power RTC with Battery-Backed SRAM and
Embedded Temp Compensation ±5ppm with Auto
Daylight Saving
ISL12022
The ISL12022 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brownout
indicator, single periodic or polled alarms, intelligent
battery-backup switching, Battery Reseal™ function and
128 bytes of battery-backed user SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Daylight Savings time adjustment is done automatically, using
parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
VBAT power, and also from VBAT to VDD power.
Applications
• Utility Meters
• POS Equipment
• Medical Devices
• Security Systems
• Vending Machines
• White Goods
• Printers and Copiers
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• On-chip Oscillator Compensation Over the Operating
Temperature Range
- ±5ppm Over -40°C to +85°C
• 10-bit Digital Temperature Sensor Output
- ±2°C Accuracy
• Customer Programmable Day Light Saving Time
• 15 Selectable Frequency Outputs
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Battery Reseal™ Function to Extend Battery Shelf Life
• Automatic Backup to Battery or Super Capacitor
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Battery Status Monitor
- 2 User Programmable Levels
- Seven Selectable Voltages for Each Level
• Power Status Brownout Monitor
- Six Selectable Trip Levels, from 2.295V to 4.675V
• Oscillator Failure Detection
• Time Stamp for First VDD to VBAT, and Last VBAT to VDD
• 128 Bytes Battery-Backed User SRAM
• I2C Bus™
- 400kHz Clock Frequency
• 1µA Typical Battery Current
• Pb-Free (RoHS Compliant)
VDD = 2.7V
TO 5.5V
CIN
0.1µF
ISL12022
VDD VBAT
GND
JBAT
DBAT
BAT43W
CBAT
0.1µF
+ VBAT = 1.8V
TO 3.2V
FIGURE 1. TYPICAL APPLICATION CIRCUIT
November 22, 2011
FN6659.3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
Intersil (and design) and Battery Reseal are trademarks owned by Intersil Corporation or one of its subsidiaries.
I2C Bus is a trademark owned by NXP Semiconductors Netherlands, B.V. All other trademarks mentioned are the property of their respective owners.
1 page  
ISL12022
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply over the
operating temperature range, -40°C to +85°C
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
(Note 13) (Note 9) (Note 13) UNITS
NOTES
VDD SR-
VDDSR+
VDD Negative Slew Rate
VDD Positive Slew Rate, Minimum
10 V/ms
0.05
V/ms
10
16
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +85°C
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP MAX
(Note 9) (Note 13) UNITS
VIL
VIH
Hysteresis
SDA and SCL Input Buffer LOW Voltage
SDA and SCL Input Buffer HIGH Voltage
SDA and SCL Input Buffer Hysteresis
VOL SDA Output Buffer LOW Voltage,
Sinking 3mA
VDD = 5V, IOL = 3mA
-0.3
0.7 x VDD
0.05 x VDD
0
0.02
0.3 x VDD
VDD + 0.3
0.4
V
V
V
V
CPIN
fSCL
tIN
SDA and SCL Pin Capacitance
SCL Frequency
TA = +25°C, f = 1MHz, VDD = 5V,
VIN = 0V, VOUT = 0V
Pulse Width Suppression Time at SDA Any pulse narrower than the max
and SCL Inputs
spec is suppressed.
10 pF
400 kHz
50 ns
tAA SCL Falling Edge To SDA Output Data SCL falling edge crossing 30% of
Valid
VDD, until SDA exits the 30% to
70% of VDD window.
tBUF Time the Bus Must be Free Before the SDA crossing 70% of VDD during
Start of a New Transmission
a STOP condition, to SDA
crossing 70% of VDD during the
following START condition.
1300
900 ns
ns
tLOW Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
tSU:STO STOP Condition Setup Time
tHD:STO STOP Condition Hold Time
tDH Output Data Hold Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
From SDA exiting the 30% to
70% of VDD window, to SCL rising
edge crossing 30% of VDD.
From SCL falling edge crossing
30% of VDD to SDA entering the
30% to 70% of VDD window.
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
From SDA rising edge to SCL
falling edge. Both crossing 70%
of VDD.
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
600
600
100
0
600
600
0
ns
ns
ns
900 ns
ns
ns
ns
NOTES
11, 12
11, 12
5 FN6659.3
November 22, 2011
5 Page 
ISL12022
Brownout Detection
The ISL12022 monitors the VDD level continuously and provides
warning if the VDD level drops below prescribed levels. There are
six (6) levels that can be selected for the trip level. These values
are 85% below popular VDD levels. The LVDD bit in the Status
Register will be set to “1” when brownout is detected. Note that
the I2C serial bus remains active unless the Battery VTRIP levels
are reached.
Battery Level Monitor
The ISL12022 has a built in warning feature once the Back-up
battery level drops first to 85% and then to 75% of the battery’s
nominal VBAT level. When the battery voltage drops to between
85% and 75%, the LBAT85 bit is set in the status register. When
the level drops below 75%, both LBAT85 and LBAT75 bits are set
in the status register.
The battery level monitor is not functional in battery backup
mode. In order to read the monitor bits after powering up VDD,
instigate a battery level measurement by setting the TSE bit to
"1" (BETA register), and then read the bits.
There is a Battery Time Stamp Function available. Once the VDD
is low enough to enable switchover to the battery, the RTC
time/date are written into the TSV2B register. This information
can be read from the TSV2B registers to discover the point in
time of the VDD power-down. If there are multiple power-down
cycles before reading these registers, the first values stored in
these registers will be retained. These registers will hold the
original power-down value until they are cleared by setting CLRTS
= 1 to clear the registers.
The normal power switching of the ISL12022 is designed to
switch into battery-backup mode only if the VDD power is lost.
This will ensure that the device can accept a wide range of
backup voltages from many types of sources while reliably
switching into backup mode.
Note that the ISL12022 is not guaranteed to operate with
VBAT < 1.8V. If the battery voltage is expected to drop lower than
this minimum, correct operation of the device, especially after a
VDD power-down cycle, is not guaranteed.
The minimum VBAT to insure SRAM is stable is 1.0V. Below that,
the SRAM may be corrupted when VDD power resumes.
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz quartz
crystal to maintain an accurate internal representation of
second, minute, hour, day of week, date, month, and year. The
RTC also has leap-year correction. The clock also corrects for
months having fewer than 31 days and has a bit that controls
24-hour or AM/PM format. When the ISL12022 powers up after
the loss of both VDD and VBAT, the clock will not begin
incrementing until at least one byte is written to the clock
register.
Single Event and Interrupt
The alarm mode is enabled via the MSB bit. Choosing single
event or interrupt alarm mode is selected via the IM bit. Note that
when the frequency output function is enabled, the alarm
function is disabled.
The standard alarm allows for alarms of time, date, day of the
week, month, and year. When a time alarm occurs in single
event mode, the IRQ/FOUT pin will be pulled low and the alarm
status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring alarm
functionality. Hence, once the alarm is set, the device will
continue to alarm for each occurring match of the alarm and
present time. Thus, it will alarm as often as every minute (if only
the nth second is set) or as infrequently as once a year (if at least
the nth month is set). During pulsed interrupt mode, the
IRQ/FOUT pin will be pulled low for 250ms and the alarm status
bit (ALM) will be set to “1”.
The ALM bit can be reset by the user or cleared automatically
using the auto reset mode (see ARST bit). The alarm function can
be enabled/disabled during battery-backup mode using the
FOBATB bit. For more information on the alarm, please see
“ALARM Registers (10h to 15h)” on page 20.
Frequency Output Mode
The ISL12022 has the option to provide a clock output signal
using the IRQ/FOUT open drain output pin. The frequency output
mode is set by using the FO bits to select 15 possible output
frequency values from 1/32Hz to 32kHz. The frequency output
can be enabled/disabled during battery-backup mode using the
FOBATB bit.
General Purpose User SRAM
The ISL12022 provides 128 bytes of user SRAM. The SRAM will
continue to operate in battery-backup mode. However, it should
be noted that the I2C bus is disabled in battery-backup mode.
I2C Serial Interface
The ISL12022 has an I2C serial bus interface that provides
access to the control and status registers and the user SRAM.
The I2C serial interface is compatible with other industry I2C
serial bus protocols using a bi-directional data signal (SDA) and a
clock signal (SCL).
Oscillator Compensation
The ISL12022 provides both initial timing correction and
temperature correction due to variation of the crystal oscillator.
Analog and digital trimming control is provided for initial
adjustment, and a temperature compensation function is
provided to automatically correct for temperature drift of the
crystal. Initial values are preset and recalled on initial power-up
for the Initial AT and DT settings (IATR, IDTR), temperature
coefficient (ALPHA), crystal capacitance (BETA), and the crystal
turn-over temperature (XTO). These initial values are typical of
units available on the market, although the user may program
specific values after testing for best accuracy. The function can
be enabled/disabled at any time and can be used in battery
mode as well.
11 FN6659.3
November 22, 2011
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ISL12022.PDF ] | |
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