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ISL12028A の電気的特性と機能

ISL12028AのメーカーはIntersilです、この部品の機能は「Real Time Clock/Calendar」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL12028A
部品説明 Real Time Clock/Calendar
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL12028A Datasheet, ISL12028A PDF,ピン配置, 機能
Data Sheet
ISL12028, ISL12028A
August 14, 2015
FN8233.10
Real Time Clock/Calendar with I2C Bus™
and EEPROM
The ISL12028 device is a low power real time clock with
clock/calendar, power-fail indicator, clock output and crystal
compensation, two periodic or polled alarms (CMOS output),
intelligent battery backup switching, CPU Supervisor,
integrated 512x8-bit EEPROM configured in 16 bytes per
page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12028 and ISL12028A Power Control Settings are
different. The ISL12028 uses the Legacy Mode Setting, and
the ISL12028A uses the Standard Mode Setting.
Applications that have VBAT > VDD will require only the
ISL12028A. Please refer to “Power Control Operation” on
page 14 for more details. Also, please refer to “I2C
Communications During Battery Backup and LVR Operation”
on page 25 for important details.
Pinout
ISL12028, ISL12028A
(14 LD TSSOP, SOIC)
TOP VIEW
X1
X2
NC
NC
NC
RESET
GND
1
2
3
4
5
6
7
14 VDD
13 VBAT
12 IRQ/FOUT
11 NC
10 NC
9 SCL
8 SDA
NC = No internal connection
Features
• Real Time Clock/Calendar
- Tracks time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or SuperCap
- Power Failure Detection
- 800nA Battery Supply Current
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8 Bits of EEPROM:
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• CPU Supervisor Functions:
- Power On Reset, Low Voltage Sense
- Watchdog Timer (0.25s, 0.75s and 1.75s)
• I2C Interface
- 400kHz Data Transfer Rate
• 14 Ld SOIC and 14 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V.
BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas LLC 2005, 2006, 2008, 2010, 2015.
All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

1 Page





ISL12028A pdf, ピン配列
ISL12028, ISL12028A
Pin Descriptions
PIN
NUMBER
SYMBOL
1 X1
2 X2
6 RESET
7 GND
8 SDA
9 SCL
12 IRQ/FOUT
13 VBAT
14
3, 4, 5, 10,
11
VDD
NC
DESCRIPTION
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
RESET is a reset signal output. This signal notifies a host processor that the “Watchdog” time period has expired or
that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended
value for the pull-up resistor is 5k. If unused, connect to ground.
Ground.
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain
output and may be wire OR’ed with other open drain or open collector outputs.
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is
always active (not gated).
Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The
function is set via the configuration register. It is a CMOS push-pull output and does not require a pull-up resistor.
This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the
VDD supply fails. This pin should be tied to ground if not used.
Power Supply.
No Internal Connection.
3 FN8233.10
August 14, 2015


3Pages


ISL12028A 電子部品, 半導体
ISL12028, ISL12028A
Serial Interface (I2C) Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 16)
MAX
TYP (Note 16) UNITS NOTES
tAA SCL Falling Edge to SDA Output SCL falling edge crossing 30% of VDD,
Data Valid
until SDA exits the 30% to 70% of VDD
window.
900 ns
tBUF
Time the bus must be free before
the start of a new transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition.
1300
ns
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STO
tDH
Cb
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
Capacitive Loading of SDA or SCL
Measured at the 30% of VDD crossing.
Measured at the 70% of VDD crossing.
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
From SDA falling edge crossing 30%
of VDD to SCL falling edge crossing
70% of VDD.
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD
From SCL falling edge crossing 70%
of VDD to SDA entering the 30% to
70% of VDD window.
From SCL rising edge crossing 70% of
VDD, to SDA rising edge crossing 30%
of VDD.
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
From SCL falling edge crossing 30%
of VDD, until SDA enters the 30% to
70% of VDD window.
Total on-chip and off-chip
1300
600
600
600
100
0
600
600
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
400 pF
Cpin SDA, and SCL Pin Capacitance
10 pF
tWC Non-volatile Write Cycle Time
tR SDA and SCL Rise Time
From 30% to 70% of VDD
tF SDA and SCL Fall Time
From 70% to 30% of VDD
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
20 + 0.1 x Cb
20 + 0.1 x Cb
10
12
20
250
250
400
ms 14
ns 15
ns 15
pF 15
RPU SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.
Off-chip
For Cb = 400pF, max is about
2k~2.5k.
For Cb = 40pF, max is about
15k~20k
1
k15
NOTES:
7. IRQ/FOUT Inactive (no frequency output and no alarms).
8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz.
9. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V.
10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT 1.8V.
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
13. Parameter is not 100% tested.
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6 FN8233.10
August 14, 2015

6 Page



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部品番号部品説明メーカ
ISL12028

Real Time Clock/Calendar

Intersil Corporation
Intersil Corporation
ISL12028A

Real Time Clock/Calendar

Intersil
Intersil


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