PDF MTFC4GACAAAM-4M-IT Data sheet ( Hoja de datos )

Número de pieza	MTFC4GACAAAM-4M-IT
Descripción	e-MMC Memory
Fabricantes	Micron
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Micron Confidential and Proprietary e·MMC Memory MTFC4GACAAAM-4M IT, MTFC8GACAAAM-4M IT 4GB, 8GB: e·MMC Features Features • MultiMediaCard (MMC) controller and NAND Flash • 153-ball VFBGA (RoHS compliant, "green" package) • VCC: 2.7–3.6V • VCCQ (dual voltage): 1.65–1.95V; 2.7–3.6V • Temperature ranges – Operating temperature: –40˚C to +85˚C – Storage temperature: –40˚C to +85˚C MMC-Specific Features • JEDEC/MMC standard version 4.51-compliant (JEDEC Standard No. 84-B451) – SPI mode not supported 1 – Advanced 11-signal interface – x1, x4, and x8 I/Os, selectable by host – SDR/DDR modes up to 52 MHz clock speed – HS200 mode – Real-time clock – Command classes: class 0 (basic); class 2 (block read); class 4 (block write); class 5 (erase); class 6 (write protection); class 7 (lock card) – Temporary write protection – Boot operation (high-speed boot) – Sleep mode – Replay-protected memory block (RPMB) – Secure erase and secure trim – Hardware reset signal – Multiple partitions with enhanced attribute – Permanent and power-on write protection – High-priority interrupt (HPI) Figure 1: Micron e·MMC Device MMC power MMC controller MMC interface NAND Flash power NAND Flash MMC-Specific Features (Continued) – Background operation – Reliable write – Discard and sanitize – Extended partitioning – Context ID – Data TAG – Packed commands – Dynamic device capacity – Backward compatible with previous MMC – Thermal specification – Cache • ECC and block management implemented Note: 1. The JEDEC specification is available at www.jedec.org/sites/default/files/docs/ JESD84-B451.pdf. PDF: 09005aef856e6fe7 emmc_ps8210_v451_80s_153b_it.pdf - Rev. E 6/14 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1 page Micron Confidential and Proprietary Signal Descriptions 4GB, 8GB: e·MMC Signal Descriptions Table 5: Signal Descriptions Symbol CLK RST_n CMD DAT[7:0] VCC VCCQ VSS1 VSSQ1 VDDIM NC RFU Type Input Input I/O I/O Supply Supply Supply Supply – – Description Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The frequency can vary between the minimum and the maximum clock frequency. Reset: The RST_n signal is used by the host for resetting the device, moving the device to the pre- idle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it. Command: This signal is a bidirectional command channel used for command and response trans- fers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating Modes). Commands are sent from the MMC host to the device, and responses are sent from the device to the host. Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By de- fault, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode) or DAT[7:0] (8-bit mode). e·MMC includes internal pull-up resistors for data lines DAT[7:1]. Immedi- ately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the DAT[7:1] lines. VCC: NAND interface (I/F) I/O and NAND Flash power supply. VCCQ: e·MMC controller core and e·MMC I/F I/O power supply. VSS: NAND I/F I/O and NAND Flash ground connection. VSSQ: e·MMC controller core and e·MMC I/F ground connection. Internal voltage node: At least a 0.1μF capacitor is required to connect VDDIM to ground. A 1μF ca- pacitor is recommended. Do not tie to supply voltage or ground. No connect: No internal connection is present. Reserved for future use: No internal connection is present. Leave it floating externally. Note: 1. VSS and VSSQ are connected internally. PDF: 09005aef856e6fe7 emmc_ps8210_v451_80s_153b_it.pdf - Rev. E 6/14 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. 5 Page Micron Confidential and Proprietary CSD Register 4GB, 8GB: e·MMC CSD Register The card-specific data (CSD) register provides information about accessing the device contents. The CSD register defines the data format, error correction type, maximum da- ta access time, and data transfer speed, as well as whether the DS register can be used. The programmable part of the register (entries marked with W or E in the following ta- ble) can be changed by the PROGRAM_CSD (CMD27) command. Table 8: CSD Register Field Parameters Name CSD structure System specification version Reserved2 Data read access time 1 Data read access time 2 in CLK cycles (NSAC × 100) Maximum bus clock frequency Card command classes3 Maximum read data block length Partial blocks for reads supported Write block misalignment Read block misalignment DSR implemented4 Reserved Device size Maximum read current at VDD,min Maximum read current at VDD,max Maximum write current at VDD,min Maximum write current at VDD,max Device size multiplier Erase group size Erase group size multiplier Write protect group size Field CSD_STRUCTURE SPEC_VERS TAAC NSAC – TRAN_SPEED CCC READ_BL_LEN READ_BL_PARTIAL WRITE_BLK_MISALIGN READ_BLK_MISALIGN DSR_IMP – C_SIZE VDD_R_CURR_MIN VDD_R_CURR_MAX VDD_W_CURR_MIN VDD_W_CURR_MAX C_SIZE_MULT ERASE_GRP_SIZE ERASE_GRP_MULT WP_GRP_SIZE Write protect group enable Manufacturer default ECC Write-speed factor Maximum write data block length Partial blocks for writes supported Reserved Content protection application WP_GRP_ENABLE DEFAULT_ECC R2W_FACTOR WRITE_BL_LEN WRITE_BL_PARTIAL – CONTENT_PROT_APP 4GB 8GB 16GB Size (Bits) 2 4 2 8 8 Cell Type1 R R – R R CSD Bits [127:126] [125:122] [121:120] [119:112] [111:104] 8 R [103:96] 12 R [95:84] 4 R [83:80] 1R [79] 1R [78] 1R [77] 1R [76] 2 – [75:74] 12 R [73:62] 3 R [61:59] 3 R [58:56] 3 R [55:53] 3 R [52:50] 3 R [49:47] 5 R [46:42] 5 R [41:37] 5 R [36:32] 1R [31] 2 R [30:29] 3 R [28:26] 4 R [25:22] 1R [21] 4 – [20:17] 1R [16] CSD Value 03h 04h – 4Fh 01h 32h 0F5h 09h 0h 0h 0h 1h – FFFh 07h 07h 07h 07h 07h 1Fh 1Fh 07h 0Fh 1Fh 1h 00h 02h 09h 0h – 0h PDF: 09005aef856e6fe7 emmc_ps8210_v451_80s_153b_it.pdf - Rev. E 6/14 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. 11 Page

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